Apparatus and associated methods relate to an I/O bank impedance calibration circuit having (a) a replica master resistor coupled to an external precision resistor, and (b) a control circuit configured to calibrate an output impedance of the master resistor to generate a calibrated code to control a replica slave resistor in each bank. In an illustrative example, a signal applied to the replica master resistor may be compared against a programmable reference signal. The control circuit may generate the calibrated code, in response to the comparison result, to calibrate the output impedance of the replica master resistor. By implementing the replica master resistor and the replica slave resistor, impedances of a large number of IOs or banks may be calibrated by the impedance calibration circuit using a single one reference pin.

A switching circuit includes a first transmission terminal, a second transmission terminal, a third transmission terminal, and a variable impedance circuit. The first and the second transmission terminals coupled to a common node form a first transmission path. The third transmission terminal coupled to the common node forms a second transmission path with the first transmission terminal. The variable impedance circuit has a first terminal coupled between the common node and the third transmission terminal, and a second terminal coupled to a first reference potential terminal. When the first transmission path transmits a first signal, a first frequency bandwidth range provided by the variable impedance circuit is determined according to a first frequency of the first signal so that the variable impedance circuit provides low impedance in the first frequency bandwidth range, and the first frequency bandwidth range covers the first frequency.

Disclosed is a transceiver which includes a logic circuit that generates parallel transmission data in response to a first test mode signal or a second test mode signal, a serializer that converts the parallel transmission data into serial transmission data, a driver that outputs the serial transmission data through transmission pads, an analog circuit that receives serial reception data through reception pads, a deserializer that converts the serial reception data into parallel reception data, a plurality of test switches switched in response to the first test mode signal, and a test circuit that is electrically connected to the analog circuit through the plurality of test switches and outputs serial post data corresponding to the serial transmission data to the analog circuit.

Main wiring including a plurality of differential transmission lines for transmitting differential signals is formed on a motherboard. Termination resistors, provided at both ends of each of the plurality of differential transmission lines, connect the plurality of differential transmission lines to each other. A plurality of daughter boards are connected in parallel to each other via the main wiring. A line characteristic impedance of each differential transmission line is higher than a termination resistance value, which is a resistance value of the termination resistor.

In an integrated circuit component having a command interface to receive commands, a data interface to receive write data during a write-data reception interval, and first and second registers, control circuitry within the integrated circuit component responds to one or more of the commands by storing within the first register and the second register, respectively, a first control value that specifies a first termination to be applied to the data interface during the write-data reception interval, and a second control value that specifies a second termination to be applied to the data interface after the write-data reception interval transpires.

Local on-die termination controllers for effecting termination of a high-speed signaling links simultaneously engage on-die termination structures within multiple integrated-circuit memory devices disposed on the same memory module, and/or within the same integrated-circuit package, and coupled to the high-speed signaling link. A termination control bus is coupled to memory devices on a module, and provides for peer-to-peer communication of termination control signals.

An electronic device includes a termination control circuit and a data input/output (I/O) circuit. The termination control circuit is configured to generate a termination enablement signal which is activated during a termination operation period for activating a termination resistor while a write operation is performed. In addition, the termination control circuit is configured to adjust a period that the termination enablement signal is activated according to whether a write command is inputted to the termination control circuit during a set detection period of the write operation. The data I/O circuit is configured to receive data by activating the termination resistor during a period that the termination enablement signal is activated when the write operation is performed.

A transmission-end impedance matching circuit operates according to a signal of an overvoltage signal source and includes a first level shifter, a voltage generating circuit, and an impedance matching circuit. The first level shifter generates a first conversion voltage according to a source signal and operates between a first high voltage and a ground voltage. The voltage generating circuit generates a second high voltage according to the first conversion voltage, the first high voltage, and a medium voltage. The impedance matching circuit includes a second level shifter, a transistor, and two resistors. The second level shifter generates a gate voltage according to the second high voltage, a low voltage, and an input signal. The transistor is turned on/off according to the gate voltage and has a withstand voltage lower than the first high voltage. Each of the two resistors is coupled between the transistor and a differential signal transmission end.

Disclosed is a transmitter which includes a channel driver that includes a pull-up transistor and a pull-down transistor connected between a power node and a ground node and outputs a voltage between the pull-up transistor and the pull-down transistor as a transmit signal, and a pre-driver that controls the pull-up transistor and the pull-down transistor in response to a driving signal and controls the channel driver such that the transmit signal is overshot at a rising edge of the driving signal and the transmit signal is undershot at a falling edge of the driving signal.

An electronic circuit includes a driving cell, one or more driven cells and one or more inverters. The driving cell has two or more inputs and at least one output and is configured to toggle the output between first and second logic states in response to the inputs. Each driven cell has two or more inputs, of which at least one input is configured to be driven by the output of the driving cell. The one or more inverters are placed in a signal network that connects the driving cell to the driven cells. The inverters are configured to balance, over the signal network, (i) a first capacitive load charged by electrical currents caused by transitions from the first logic state to the second logic state and (ii) a second capacitive load charged by electrical currents caused by transitions from the second logic state to the first logic state.