A memory device includes a pad region having a flag pad separated from an external host, and a signal pad connected to the external host. A bank region is provided having a plurality of memory cells therein. An on-die-termination (ODT) setting circuit is provided, which is configured to receive a control command including first data corresponding to termination resistance requested by the host, and a ODT enable signal. The setting circuit is configured to generate second data corresponding to the ODT resistance. An ODT enable circuit is provided, which is configured to output an ODT flag signal to the flag pad, in response to the control command and the ODT enable signal. A resistor circuit is provided, which is configured to connect the ODT resistance to the signal pad using the second data.

A transmitter device includes a transmitter circuit, a voltage generator circuit, and a calibration circuit. The transmitter circuit is configured to selectively operate in a calibration mode or a normal mode in response to a first control signal, in which the transmitter circuit has a first output terminal and a second output terminal. The voltage generator circuit is configured to generate a bias voltage, in which the bias voltage has a first level in the calibration mode and has a second level in the normal mode, and the first level is different from the second level. The calibration circuit is configured to be turned on in the calibration mode according to the bias voltage and a second control signal, in order to calibrate a level of the first output terminal and a level of the second output terminal.

Systems, apparatuses, and methods for conveying and receiving information as electrical signals in a computing system are disclosed. A computing system includes multiple transmitters sending singled-ended data signals to multiple receivers. A termination voltage is generated and sent to the multiple receivers. The termination voltage is coupled to each of signal termination circuitry and signal sampling circuitry within each of the multiple receivers. Any change in the termination voltage affects the termination circuitry and affects comparisons performed by the sampling circuitry. Received signals are reconstructed at the receivers using the received signals, the signal termination circuitry and the signal sampling circuitry.

A semiconductor apparatus includes a calibration circuit and a main driver. The calibration circuit is configured to generate a first calibration code when set to have a positive offset and generate a second calibration code when set to have a negative offset complementary to the positive offset. The main driver is configured to set a resistance value of the main driver based on the first and second calibration codes.

A memory device includes a calibration circuit having a pull-up code generator including a pull-up resistor block and generating a pull-up code, and a pull-down code generator including a replica pull-up resistor block and a pull-down resistor block and generating a pull-down code, and an off chip driver/on die termination circuit providing a termination resistance having a resistance value set by the calibration circuit in a data reception operation and outputting data at an output strength set by the calibration circuit in a data output operation. In a calibration operation, a resistance value of the replica pull-up resistor block is adjusted to be less than a resistance value of the pull-up resistor block, and the pull-down code has a code value by which a resistance value of the pull-down resistor block corresponds to the resistance value of the replica pull-up resistor block.

Memory devices and systems with per pin input/output termination and driver impedance calibration capabilities, and associated methods, are disclosed herein. In one embodiment, a device apparatus includes circuitry dedicated to an individual DQ pin of the device apparatus. The circuitry can be configured to (i) generate, at least in part, a voltage at the DQ pin based, at least in part, on an impedance internal to a host device electrically connected to the device apparatus and (ii) compare the voltage to a target voltage. Based, at least in part, on the comparison, the circuitry can be configured to adjust a resistance of an output driver and/or a termination circuit of the device apparatus that correspond to the DQ pin to adjust the impedance of the output driver and/or termination circuit to match an impedance associated with a corresponding input/output pin of the host device.

Described are integrated-circuit die with differential receivers, the inputs of which are coupled to external signal pads. Termination legs coupled to the signal pads support multiple termination topologies. These termination legs can support adjustable impedances, capacitances, or both, which may be controlled using an integrated memory.

In an embodiment, a method includes programming a control signal that specifies a target resistance and a target voltage in a circuit. The method further includes sending the control signal to at least one transistor configured to control a current flow in the circuit. The method further includes providing, as an output, a signal with the target voltage and target resistance.

An input/output driving circuit may include a pad, an open-drain driving circuit, a high-voltage protection unit and a control unit. The open-drain driving circuit may be configured to output a transmission signal to the pad. The high-voltage protection unit may be configured to input a received signal from the pad. The control unit may include a gate control logic, a transmission control logic and an inverter for controlling the open-drain driving circuit. The control unit may also include a reception control logic and a well voltage generation unit for controlling the high-voltage protection unit.

A memory device comprising: a plurality of memories, a plurality of access units and a controller configured to control data from an access unit according to operation cycle different to another access unit whose form factor is different to that of the access unit.