A calibration circuit includes an oscillator configured to generate an oscillation signal according to a control voltage; a counter configured to generate a count value according to the oscillation signal; and a control circuit configured to control a pull-up driver and a pull-down driver commonly coupled to an output node according to the count value, wherein the control circuit compares a reference count value of the counter by providing a reference voltage as the control voltage for a unit control period with a count value of the counter by providing an output voltage of the output node as the control voltage for a unit control period, and controls a pull-up control signal that adjusts turn-on impedance of the pull-up driver and a pull-down control signal that adjusts turn-on impedance of the pull-down driver.

An impedance calibration circuit includes a first code generation circuit connected to a first reference resistor, and configured to generate a first code for forming a resistance based on the first reference resistor, by using the first reference resistor; a second code generation circuit configured to form a resistance of a second reference resistor less than the resistance of the first reference resistor, based on the first code, and generate a second code by using the second reference resistor; and a target impedance code generation circuit configured to generate a target impedance code based on the first code, the second code, and a target impedance value, and form an impedance having the target impedance value in a termination driver connected to the impedance calibration circuit, based on the target impedance code.

Described are integrated-circuit die with differential receivers, the inputs of which are coupled to external signal pads. Termination legs coupled to the signal pads support multiple termination topologies. These termination legs can support adjustable impedances, capacitances, or both, which may be controlled using an integrated memory.

Apparatuses and methods for identifying memory devices of a semiconductor device sharing an external resistance are disclosed. A memory device of a semiconductor device may be set in an identification mode and provide an identification request to other memory devices that are coupled to a common communication channel. The memory devices that are coupled to the common communication channel may share an external resistance, for example, for calibration of respective programmable termination components of the memory devices. The memory devices that receive the identification request set a respective identification flag which can be read to determine which memory devices share an external resistance with the memory device having the set identification mode.

A Controller Area Network, CAN, device, (400) is described that includes: a CAN transmitter (430) connected to two CAN bus terminals (401, 402) of the CAN device (400); a receiver circuit (450) operably coupled to the two CAN bus terminals (401, 402) of the CAN device (400); and a controller (432) connected to the CAN transmitter (430). The controller (432) is configured to: determine whether the CAN device (400) is operating as a transmitter node or a receiver node; detect a transition of the CAN device (400) from a dominant state to a recessive state; and in response to detecting both a transition of the CAN device (400) from the dominant state to the recessive state, and the determination of whether the CAN device (400) is operating as a transmitter node or a receiver node, control an output impedance of the CAN transmitter (430) to be within an impedance value range whilst a differential driver voltage on a CAN bus (104, 304, 404) connected to the CAN device (400) decreases to a predefined voltage.

Disclosed is an electronic device. The electronic device may include a printed circuit board (PCB) including at least one conducting wire, a first integrated circuit (IC) placed on the printed circuit board and including a transmit pin electrically connected to the at least one conducting wire, and a second IC placed on the printed circuit board and including a receive pin electrically connected to the at least one conducting wire, wherein the first IC is configured to transmit a specified signal having a first voltage through the transmit pin, and change an internal impedance of the first IC based on a reflected signal of the specified signal at a first time point.

On-die termination (ODT) is triggered through a serial signal encoding on an ODT signal line instead of a simple binary enable signal. An ODT circuit applies one of multiple termination impedances based on the ODT signal encoding. An ODT enable signal line receives an ODT enable signal as multiple serial bits to encode the selected termination impedance, to cause the ODT circuit to apply the selected termination impedance.

An impedance calibration circuit includes a first code generation circuit connected to a first reference resistor, and configured to generate a first code for forming a resistance based on the first reference resistor, by using the first reference resistor; a second code generation circuit configured to form a resistance of a second reference resistor less than the resistance of the first reference resistor, based on the first code, and generate a second code by using the second reference resistor; and a target impedance code generation circuit configured to generate a target impedance code based on the first code, the second code, and a target impedance value, and form an impedance having the target impedance value in a termination driver connected to the impedance calibration circuit, based on the target impedance code.

An impedance calibration circuit may include: a first driver having an impedance calibrated according to a first impedance control code, and configured to drive an output terminal according to first data; a second driver having an impedance calibrated according to a second impedance control code, and configured to drive the output terminal according to second data; and an impedance calibration circuit configured to calibrate the first impedance control code to a first target value set to a resistance value of an external resistor, and calibrate the second impedance control code to a second target value different from the resistance value of the external resistor.

A data transmitter includes: a plurality of parallel driver slices, a first slice of the plurality of parallel driver slices having a first signal generator circuit with a first transistor coupled to a data signal and in series with a second transistor coupled to a first bias signal; and a first bias circuit including a third transistor and a fourth transistor in series with a first current source, the first bias circuit further including a first operational amplifier (op amp) having a first input coupled to a first reference voltage and a second input coupled between the fourth transistor and the first current source, an output of the first op amp configured to provide the first bias signal to the second transistor and to the third transistor.