A die-to-die data transmitter is disclosed with a pull-up one-shot circuit and a pull-down one-shot circuit, each forming a delay circuit that determines a variable preemphasis period.

A voltage-mode transmitter includes a calibration circuit having a replica circuit. By adjusting a feedback voltage driving a gate of a replica transistor in the replica circuit so that an impedance of the replica circuit matches an impedance of a variable resistor, the calibration circuit calibrates an output impedance of a single slice driver.

A driver for a shared bus, such as a LIN bus, having a supply node (Vbat), a bus node (LIN), a transmit data input node (TX) and a receive data output node (RX), said driver comprising: a pull-up circuitry between the supply node and the bus node, driver circuitry (100) having a control input connected to the transmit data input node, feedback circuitry (200) configured to provide feedback from the shared bus to the control input of the driver circuitry; said feedback circuitry comprising copy circuitry (210) configured to obtain at least one copy signal representative for a signal on the bus node, filter circuitry (220) configured to low-pass filter the at least one copy signal, derivative circuitry (230) configured to obtain at least one derivative signal representative for the speed at which the signal on the bus node varies.

A device includes a power supply line, an output terminal, a circuit configured to perform a logic operation on a first signal and a second signal to produce a third signal, first, second and third transistors. The first transistor is coupled between the power supply line and the output terminal and includes a control gate supplied with the third signal. The second and third transistors are coupled in series between the power supply line and the output terminal. The second transistor includes a control gate supplied with the first signal and the third transistor includes a control gate supplied with a fourth signal that is different from each of the first, second and third signals.

An integrated circuit chip includes at least one driver circuit of single-ended structure and the first drive circuit, the first drive circuit and the at least one driver circuit of single-ended structure have the same structure, the first drive circuit includes a plurality of parallel-connected PMOS tubes and a plurality of parallel-connected NMOS tubes, the plurality of parallel-connected PMOS tubes connect the plurality of parallel-connected NMOS tube in series at a first node. After impedance calibration has been conducted, the chip confines a first impedance calibration code and a second impedance calibration code, and controls the at least one driver according to the first impedance calibration code and the second impedance calibration code; the first reference voltage is preferably configured to ¾ times of the supply voltage V.sub.DD, and the second reference voltage is preferably configured to ¼ times of the supply voltage V.sub.DD.

A switch cell structure includes a switch cell of a first type, which includes a master switch cell and a plurality of slave switch cells. The master switch cell includes a buffer having an input and an output and a transistor having a gate coupled to the output of the buffer. The slave switch cell includes a respective signal line having an input and output and a transistor having a gate coupled to the signal line, the signal lines of the slave switch cells are coupled to one another, with the output of one coupled to the input of another of the signal lines. The output of the buffer of the master switch cell is coupled to an input of one of the signal lines of slave switch cells to drive the plurality of slave switch cells.

An impedance calibration device for a semiconductor device includes a process sensor that detects a process condition for the semiconductor device and outputs a process signal, a temperature monitoring sensor that detects a temperature of the semiconductor device and outputs a temperature signal, a converter that converts the process signal and the temperature signal into a digital signal, and a code generation circuit that generates and outputs a driving code for controlling a level of a voltage at an output node according to the digital signal of the converter and a data signal. The impedance calibration device further includes an output driver that pulls up or pulls down the voltage at the output node according to the driving code.

A biased impedance circuit, an impedance adjustment circuit, and an associated signal generator are provided. The biased impedance circuit is coupled to a summation node and applies a biased impedance to the summation node. A periodic input signal is received at the summation node. The biased impedance circuit includes a switching circuit for receiving an output window signal, wherein a period of the output window signal is shorter than a period of the periodic input signal. The switching circuit includes a low impedance path and a high impedance path. The low impedance sets the biased impedance to a first impedance when the output window signal is at a first voltage level. The high impedance path sets the biased impedance to a second impedance when the output window signal is at a second voltage level. The first impedance is less than the second impedance.

A system, a method and circuit arrangements for adjusting an output impedance of an electric circuit involve impedance cells connected to an output terminal in parallel with one another. Each impedance cell includes parallel branches. Each branch includes switching units and resistors. The resistors in a branch are connected in series and contribute to an overall impedance of their corresponding impedance cell. Each switching unit is configurable to selectively bypass a corresponding one of the resistors, thereby calibrating the impedance cell. The output impedance can be set by identifying a combination of calibrated impedance cells that need to be activated in order to produce the target output impedance.

A device may include a ZQ calibration circuit. The ZQ calibration circuit may include a first register configured to store a first impedance code generated responsive to a ZQ calibration command. The ZQ calibration circuit may also include a second register configured to store a shift value. Further, the ZQ calibration circuit may include a compute block configured to generate a second impedance code based on the first impedance code and the shift value. Systems and related methods of operation are also described.