A circuit may include an output circuit with an output circuit output impedance and a control circuit. The output circuit may include a driver circuit that includes an output terminal and a driver circuit output impedance at the output terminal. The output circuit may also include an adjustable impedance circuit that includes an adjustable impedance. The adjustable impedance circuit may be coupled between the output terminal of the driver circuit and a signal transmission line. The output circuit output impedance may be based on the driver circuit output impedance and the adjustable impedance. The control circuit may be coupled to the adjustable impedance circuit. The control circuit may be configured to adjust the adjustable impedance of the adjustable impedance circuit such that the output circuit output impedance approximately equals a particular impedance.

A driver circuit for driving a transmission line includes a voltage driver and a current driver. The voltage driver is for driving the transmission line with a first voltage gain in a first operation mode. The current driver is activatable in a second operation mode for driving, together with the voltage driver, the transmission line with a second voltage gain. The transmission line may be an Ethernet-over-copper transmission line with electrical data signals from a data generator.

A transmitter is provided with a plurality of pull-up legs and a plurality of pull-down legs. A controller controls the pull-up legs and the pull-down legs so that a constant output impedance is provided while supporting a range of logic-high output voltages.

The present invention addresses the problem of many man-hours being required for a hardware engineer to adjust a resistance value such that the rise time of a signal input to an LSI body falls within a defined range. To solve this problem, the present invention provides a control circuit provided with: a conductive wire for transmitting an input electric signal to an integrated circuit; a resistance circuit which has a variable resistance value and which is connected to the conductive wire and grounded; a measurement means for measuring a rise time of the electric signal transmitted through the conductive wire, that is, the amount of time it takes for the voltage value of the electric signal to reach a predetermined second voltage value from a predetermined first voltage value, said predetermined second voltage value being higher than the first voltage value; and a control means for changing the resistance value of the resistance circuit to a value which is lower by a specific amount when the time measured by the measurement means is shorter than the minimum time of a predetermined time range, and changing the resistance value to a value which is higher by a specific amount when the time measured by the measurement means is longer than the maximum time of the predetermined time range. The control means outputs a predetermined signal upon having changed the resistance value a predetermined number of times.

A method of operating a storage device including first and second memory devices and a memory controller, which are connected to a single channel, the method including: transmitting first data output from the first memory device to the memory controller through a data signal line in the single channel; and transmitting a command to the second memory device through the data signal line while the memory controller receives the first data, wherein a voltage level of the data signal line is based on the command and the first data of the first memory device is loaded on the data signal line, and the first data and the command are transmitted in both directions of the data signal line.

The disclosed apparatuses and method provide transmission line termination. An apparatus include a stack of uniform memory dies and a storage controller. Each uniform memory die in the stack of uniform memory dies couples to a transmission line in series through wire bonds to form a transmission path. Each memory die includes an on-die termination resistance circuit connected to the transmission line. The on-die termination resistance circuit provides a minimum termination resistance. The storage controller addresses a target uniform memory die of the for an operation. The storage controller enables the on-die termination resistance circuits of a plurality of uniform memory dies along the transmission path. The storage controller transmits a data signal for the operation to the target uniform memory die with the on-die termination resistance circuit enabled for the plurality of uniform memory dies.

Local on-die termination controllers for effecting termination of a high-speed signaling links simultaneously engage on-die termination structures within multiple integrated-circuit memory devices disposed on the same memory module, and/or within the same integrated-circuit package, and coupled to the high-speed signaling link. A termination control bus is coupled to memory devices on a module, and provides for peer-to-peer communication of termination control signals.

A data transmitter includes: a plurality of parallel driver slices, a first slice of the plurality of parallel driver slices having a first signal generator circuit with a first transistor coupled to a data signal and in series with a second transistor coupled to a first bias signal; and a first bias circuit including a third transistor and a fourth transistor in series with a first current source, the first bias circuit further including a first operational amplifier (op amp) having a first input coupled to a first reference voltage and a second input coupled between the fourth transistor and the first current source, an output of the first op amp configured to provide the first bias signal to the second transistor and to the third transistor.

An on die termination (ODT) circuit includes a signal input terminal; a grounding terminal; a first transistor including a control terminal and a first terminal which are electrically connected with the signal input terminal, and a second terminal electrically connected with the grounding terminal; and a second transistor including a control terminal electrically connected with the signal input terminal, a first terminal, and a second terminal electrically connected with the grounding terminal, and when voltage of the signal input terminal changes, the first transistor has a change trend of resistance opposite to that of the second transistor.

A hybrid voltage mode (VM) and current mode (CM) four-level pulse amplitude modulation (PAM-4) transmitter circuits (a.k.a. drivers) is calibrated using a configurable replica circuit and calibration control circuitry. The replica circuit includes an on-chip termination impedance to mimic a receiver's termination impedance. The amount of level enhancement provided by the current mode circuitry is calibrated by adjusting the current provided to the output node and sunk from the output node by the replica current mode circuitry while the replica voltage mode circuitry is driving an intermediate PAM-4 level. After the level enhancement has been set, the non-linearity between levels is calibrated by adjusting the amount of current provided to the output node by the replica current mode circuitry while the replica voltage mode circuitry is driving a maximum output voltage level.