A device including an input configured to receive an input signal in an operational mode and to receive a reference voltage in a calibration mode is provided. The device includes a capacitor to store a reference charge based on the reference voltage and an input inverter to capture a transition of the input signal. The input inverter is coupled in series with the capacitor so that the transition of the input signal occurs when a voltage of the input signal crosses the reference voltage. The device includes an output inverter coupled in series with the input inverter to provide an output signal having a parity of the input signal. A system including the above device, and a method for calibrating the above device, are also provided.

A semiconductor device with a novel structure is provided. A semiconductor device with reduced power consumption is provided. A circuit which is configured to supply a signal from an input terminal to both a gate and a backgate of a transistor in a first state and to only the gate in a second state is provided. With this structure, a current supply capability of the transistor can be changed between operations; accordingly, power consumption can be reduced by the amount needed to charge the backgate.

A serial, half-duplex start/stop event detection circuit comprises a stop detection flip-flop clocked by a serial data input that takes a serial clock input as an input and generates a stop signal output indicative of a stop event. A start detection flip-flop, clocked by an inverted copy of the serial data input, takes the serial clock input as an input and generates a start signal output indicative of a start event. A first buffer flip-flop, clocked by an inverted copy of the serial clock input, takes the start signal output as an input and generates a first delayed start signal output. Similarly, a second buffer flip-flop, clocked by the serial clock input, takes the first delayed start signal output as an input and generates a second delayed start signal output. The second delayed start signal output resets at least one of said stop detection, start detection or first buffer flip-flops.

The present disclosure relates to methods and circuits to lowering the signal range of switching or logic circuits below supply range. The circuits may have one or more stages. The supply levels can be set individually for each stage. This may realize amplifiers/attenuators, both digitally and analogically controlled, based on progression and/or modulation in the supply range from stage to stage. A chain of stages can provide the desired power gain by setting the supply progression according to the nature of the incoming signals. The signal levels are lowered by generic device networks comprising voltage sources providing voltages independent of currents flowing through. Decoupling the signal amplitude from DC biasing allows for the signal swing to be lower than threshold voltages of the active devices.

According to an embodiment of the invention there is provided a device and method. The device may include a pure memristive logic gate, wherein the pure memristive logic gate consists essentially of at least one input memristive device and an output memristive device that is coupled to and differs from the at least one memristive device; wherein the pure memristive device is controlled by a single control voltage.

In accordance with an embodiment, a circuit includes a plurality of comparators disposed on an integrated circuit, the plurality of comparators having inputs coupled to a monitored power supply line; and a voting circuit having inputs coupled to outputs of the plurality of comparators. An output of the voting circuit is configured to provide a signal indicative of a brown out condition of a power source coupled to the monitored power supply line.

A three-dimensional integrated circuit having a dual or multiple power domain is capable of less energy consumption operation under a given clock rate, which results in an enhanced power-performance-area (PPA) envelope. Sequential logic operates under a system clock that determines the system throughput, whereas combinational logic operates in a different power domain to control overall system power including dynamic and static power. The sequential logic and clock network may be implemented in one tier of the three-dimensional integrated circuit supplied with a relatively high power supply voltage, whereas the combinational logic may be implemented in another tier of the three-dimensional integrated circuit supplied with a relatively low power supply voltage. Further pipeline reorganization may be implemented to leverage the system energy consumption and performance to an optimal point.

A semiconductor device with a novel structure is provided. A semiconductor device with reduced power consumption is provided. A circuit which is configured to supply a signal from an input terminal to both a gate and a backgate of a transistor in a first state and to only the gate in a second state is provided. With this structure, a current supply capability of the transistor can be changed between operations; accordingly, power consumption can be reduced by the amount needed to charge the backgate.

A logic circuit includes an input terminal for receiving an input signal, a first output terminal for outputting a first output signal, a second output terminal for outputting a second output signal, and three inverting circuits. A first inverting circuit is coupled between the input terminal and the first output terminal and includes a first depletion mode transistor. The first depletion mode transistor includes a second terminal coupled to a first node. A second inverting circuit is coupled between the first inverting circuit and the first output terminal and includes a second depletion mode transistor. The second depletion mode transistor includes a second terminal coupled to a second node. A third inverting circuit is coupled between the input terminal and the second output terminal. A first node voltage at the first node is lower than a second node voltage at the second node.

A device includes a memristive element; and a write circuit to write the memristive element into a memristive state of a plurality of memristive states by a write operation, wherein the memristive state has a characteristic flux and/or a characteristic charge; wherein the characteristic flux corresponds to a characteristic voltage drop over the memristive element applied for a saturation time and wherein the characteristic charge corresponds to a characteristic current through the memristive element applied for a saturation time; wherein the write operation includes: causing a write voltage drop over the memristive element that is greater than the characteristic voltage drop associated with the memristive state or causing a write current through the memristive element that is higher than the characteristic write current associated with the memristive state, each for a total write time that is shorter than the saturation time.