A logic circuit includes an input terminal for receiving an input signal, a first output terminal for outputting a first output signal, a second output terminal for outputting a second output signal, and three inverting circuits. A first inverting circuit is coupled between the input terminal and the first output terminal and includes a first depletion mode transistor. The first depletion mode transistor includes a second terminal coupled to a first node. A second inverting circuit is coupled between the first inverting circuit and the first output terminal and includes a second depletion mode transistor. The second depletion mode transistor includes a second terminal coupled to a second node. A third inverting circuit is coupled between the input terminal and the second output terminal. A first node voltage at the first node is lower than a second node voltage at the second node.

According to various aspects, a device is provided including: a memristive element; and a write circuit to write the memristive element into a memristive state of a plurality of memristive states by a write operation, wherein the memristive state has a characteristic flux and/or a characteristic charge associated therewith, wherein the characteristic flux corresponds to a characteristic voltage drop over the memristive element applied for a saturation time and wherein the characteristic charge corresponds to a characteristic current through the memristive element applied for a saturation time; wherein the write operation includes: causing a write voltage drop over the memristive element that is greater than the characteristic voltage drop associated with the memristive state for a total write time that is shorter than the saturation time, or causing a write current through the memristive element that is higher than the characteristic write current associated with the memristive state for a total write time that is shorter than the saturation time.

An embodiment relates to a method for manufacturing a metal nanosheet, including: providing a template having a two-dimensional layered structure with a limited interlayer height; and electroplating metal in an interlayer space of the template, wherein nucleation occurs in the interlayer space of the template, and the interlayer height is fixed.