Various implementations described herein are related to a device having a level shifter that receives an input signal and reference voltages and provides level-shifted input signals based on the reference voltages. The device may have a pre-driver that receives the level-shifted input signals and reference voltages and provides gate voltages based on the reference voltages. The device may have a gate stabilizer that receives the reference voltages and provides a stabilized reference voltage based on the reference voltages. The device may have an output driver that receives the reference voltages, receives the gate voltages, receives the stabilized reference voltage and provides an output pad voltage to an input-output pad based on the reference voltages, the gate voltages and the stabilized reference voltage.

Various implementations described herein are related to a device having a level shifter that receives an input signal and reference voltages and provides level-shifted input signals based on the reference voltages. The device may have a pre-driver that receives the level-shifted input signals and reference voltages and provides gate voltages based on the reference voltages. The device may have a gate stabilizer that receives the reference voltages and provides a stabilized reference voltage based on the reference voltages. The device may have an output driver that receives the reference voltages, receives the gate voltages, receives the stabilized reference voltage and provides an output pad voltage to an input-output pad based on the reference voltages, the gate voltages and the stabilized reference voltage.

A circuit provides fail safe protection of an input/output (I/O) circuit of a chip. The I/O circuit comprises an I/O pad connected to one or more other chips via an I/O bus. The circuit comprise a supply and failsafe detector component. The supply and failsafe detector component generates an I/O supply output signal. The I/O supply output signal has a low voltage value when the I/O supply voltage of the chip is below a medium voltage level and the I/O supply output signal having a high voltage value when the I/O supply voltage of the chip is above the medium voltage level. The medium voltage is above a threshold voltage of the transistor of the I/O circuit and below the high voltage value. The circuit uses the I/O supply output signal to provide a reference voltage as input to the transistor of the I/O circuit.

A circuit provides fail safe protection of an input/output (I/O) circuit of a chip. The I/O circuit comprises an I/O pad connected to one or more other chips via an I/O bus. The circuit comprise a supply and failsafe detector component. The supply and failsafe detector component generates an I/O supply output signal. The I/O supply output signal has a low voltage value when the I/O supply voltage of the chip is below a medium voltage level and the I/O supply output signal having a high voltage value when the I/O supply voltage of the chip is above the medium voltage level. The medium voltage is above a threshold voltage of the transistor of the I/O circuit and below the high voltage value. The circuit uses the I/O supply output signal to provide a reference voltage as input to the transistor of the I/O circuit.

A semiconductor device according to an aspect of the present disclosure includes: a plurality of line layers; a first line; and a second line that is not connected to the first line and is redundantly provided to transfer a signal having a level same as a level of a signal transferred through the first line. The first line and the second line are included in different layers out of the plurality of line layers, and a distance between the first line and the second line is longer than an interlayer distance between line layers next to each other out of the plurality of line layers.

A monitor circuit (301) for monitoring changes in an input digital value of a register circuit comprises a data input (302) configured to receive a copy of the input digital value of said register circuit, and one or more triggering signal inputs (303) configured to receive one or more triggering signals. One or more triggering edges thereof define an allowable time limit before which a digital value must appear at a data input of said register circuit to become properly stored in said register circuit. The monitor circuit comprises a data event (DE) output (305), so that said monitor circuit is configured to produce a DE signal at said DE output (305) in response to a digital value at said data input (302) changing within a time window defined by said one or more triggering signals.

A digital integrated circuit comprising a logic array comprises a functional logic block, a logic unit for detecting transient errors affecting the functional logic block, an input FIFO memory for supplying the functional logic block with samples, an output FIFO memory for receiving samples output from the functional logic block, a buffer memory that is supplied with samples by the input FIFO memory, and a logic control unit that is able to control read access to the input FIFO memory and write access to the output FIFO memory and that is configured, when an error is detected by the transient-error-detecting logic unit, to reset the transient-error-detecting logic unit and the functional logic block, to suspend write access to the output FIFO memory and to switch the input of the functional logic block to the output of the buffer memory.

A digital integrated circuit comprising a logic array comprises a functional logic block, a logic unit for detecting transient errors affecting the functional logic block, an input FIFO memory for supplying the functional logic block with samples, an output FIFO memory for receiving samples output from the functional logic block, a buffer memory that is supplied with samples by the input FIFO memory, and a logic control unit that is able to control read access to the input FIFO memory and write access to the output FIFO memory and that is configured, when an error is detected by the transient-error-detecting logic unit, to reset the transient-error-detecting logic unit and the functional logic block, to suspend write access to the output FIFO memory and to switch the input of the functional logic block to the output of the buffer memory.

A buffer circuit includes a first MOSFET including a first source electrode, a first gate electrode, and a first drain electrode, and a second MOSFET, which includes a second source electrode, a second gate electrode, and a second drain electrode, and is same in polarity as the first MOSFET, and the first gate electrode and the second gate electrode are electrically connected to each other.

The present invention relates to an ultrasound beam quality test apparatus and methods of use. In this regard, fetal heart rate (FHR) transducer is placed for test and interconnected with fetal monitors. Phantoms of different heights can be placed on the FHR transducer. A computer system includes a beam control circuit. A plurality of hydrophone piezo-electric crystal (PZT) discs are placed on top of the phantom and interconnected with the beam control circuit. The computer system analyzes the ultrasound beam quality, of the FHR transducer, as it passes through the phantom. The beam control circuit can also control the oscillating motion of a metal plate to simulate a fetal heart beat by way of a linear actuator. The FHR transducer registered heartbeat, by way of the fetal monitor, is then compared to the simulated fetal heart beat to determine if the FHR transducer is working correctly.