Push-pull integrated circuit output drivers may interfere with communication by other entities on a bus when an integrated circuit is powered down. When there is no power and/or when the bonding pad is externally driven above the internal supply voltage, the substrate/body/well of the p-channel field effect transistor (PFET) of the output driver is biased to prevent its drain diode from becoming forward biased thereby preventing interference with communication on the bus. Also, when there is no power, driver is powered down or pull up is disabled, the gate of the driver PFET is driven to a voltage that ensures the driver PFET remains off when the bonding pad is externally driven above the internal supply voltage.

Push-pull integrated circuit output drivers may interfere with communication by other entities on a bus when an integrated circuit is powered down. When there is no power and/or when the bonding pad is externally driven above the internal supply voltage, the substrate/body/well of the p-channel field effect transistor (PFET) of the output driver is biased to prevent its drain diode from becoming forward biased thereby preventing interference with communication on the bus. Also, when there is no power, driver is powered down or pull up is disabled, the gate of the driver PFET is driven to a voltage that ensures the driver PFET remains off when the bonding pad is externally driven above the internal supply voltage.

According to an embodiment of the present disclosure, a semiconductor memory device includes a mode register circuit including a plurality of write mode register sets for providing a plurality of setting codes or a plurality of monitoring codes; and a defect detection circuit suitable for outputting a defect determination signal by detecting any defect in the mode register circuit, based on the plurality of monitoring codes, wherein each of the write mode register sets includes: a storing circuit suitable for storing an operational code according to a mode register write command; and an output control circuit suitable for outputting the stored operational code in the storing circuit as a corresponding setting code, or inverting the stored operational code in the storing circuit to output a corresponding monitoring code, according to a test mode signal.

An apparatus includes an integrated circuit and a plurality of conducting wires disposed on the integrated circuit. The integrated circuit includes: (i) a signal generation circuit, which is configured to generate random signal and selection signal based on random or pseudo-random numbers, (ii) a transmitting circuit configured to select at least one from among the plurality of conducting wires based on the selection signal and to output the random signal through the at least one conducting wire, and (iii) a receiving circuit configured to detect an invasive attack on the integrated circuit based on signal received through the at least one conducting wire.

The present invention provides an output buffer including a first transistor, a second transistor and a pad-tracking circuit is disclosed. The first transistor is coupled between a supply voltage and an output node, wherein the output node is coupled to a pad. The second transistor is coupled between the output node and a reference voltage. The pad-tracking circuit is coupled to the control circuit and the first transistor, and is configured to generate a gate control signal to a gate electrode of the first transistor. The output buffer is selectively operated in an input mode and a fail-safe mode, and when the output buffer switches between the input mode and the fail-safe mode and the supply voltage of the first transistor ramps up or ramps down, the pad-tracking circuit generates the gate control signal to the gate electrode of the first transistor according to the voltage of the pad.

The present invention provides an output buffer including a first transistor, a second transistor and a pad-tracking circuit is disclosed. The first transistor is coupled between a supply voltage and an output node, wherein the output node is coupled to a pad. The second transistor is coupled between the output node and a reference voltage. The pad-tracking circuit is coupled to the control circuit and the first transistor, and is configured to generate a gate control signal to a gate electrode of the first transistor. The output buffer is selectively operated in an input mode and a fail-safe mode, and when the output buffer switches between the input mode and the fail-safe mode and the supply voltage of the first transistor ramps up or ramps down, the pad-tracking circuit generates the gate control signal to the gate electrode of the first transistor according to the voltage of the pad.

A System-on-Chip includes a first partition configured to implement a first application using of at least a first portion of one or more of a plurality of subsystems of the System-on-Chip and a second partition configured to implement a second application concurrently with the first partition. The second application uses at least a second portion of one or more of the plurality of subsystems. The first partition is isolated from the second partition.

Fault detection circuitry and a corresponding method are disclosed. A count value that is indicative of the switching period of a PWM signal is determined and it is determined whether this count value is between a first threshold and a second threshold. An error signal is generated when the switching period is not between the first and the second threshold. A count value that is indicative of the switch-on duration of the PWM signal is determined and compared with a switch-on threshold in order to determine whether the switch-on duration is greater than a maximum switch-on duration. A count value that is indicative of the switch-off duration of the PWM signal is determined and compared with a switch-off threshold in order to determine whether the switch-off duration is greater than a maximum switch-off duration. Error signals can be generated when the durations are greater than the maximum durations.

Integrated circuits such as application specific integrated circuits or programmable logic devices may include multiple copies of a same circuit together with a majority vote circuit in a configuration that is sometimes also referred to as multi-mode redundancy. An adder circuit may be coupled to these multiple copies and produce a carry-out signal and a sum signal based on signals received from the multiple copies. The carry-out signal of the adder circuit may provide the result of the majority vote operation. A logic exclusive OR gate may perform a logic exclusive OR operation between the sum signal and the carry-out signal, thereby generating an error signal. The error signal may indicate that one of the multiple copies produces an output that is different than the outputs produced by the other copies.

An electronic device includes a driver that is connected with a pin, receives an input signal, and outputs an output signal to the pin in response to the input signal, a core circuit that transfers the input signal to the driver, and a monitor circuit that receives the input and output signals and detects a stuck voltage state of the output signal based on the input and output signals. The monitor circuit includes a first detection circuit that detects the stuck voltage state when the input and output signals are logically incorrect, a second detection circuit that detects the stuck voltage state when the input and output signals are logically correct and when the output signal is at a low level, and a third detection circuit that detects the stuck voltage state when the input and output signals are logically correct and when the output signal is at a high level.