A trim/test interface in a packaged integrated circuit device prevents high through-current between pins of the IC device and trim/test interface digital logic within the IC device using a floating-pin-tolerant always-on CMOS input buffer. The always-on buffer uses a coupling capacitor at its input to block signals at DC and a weak-latch feedback path to ensure that intermediate or floating inputs are provided through the buffer only at one of two digital levels (e.g., those provided by a ground pin GND and by a high supply voltage pin VDD). The described interfaces and methods provide for false-entry-free test mode activation for IC devices with a low pin count, where there are a limited number of pins to cover all test/trim functions, or in which only analog, no-connect, or failsafe pins are available for trim or test mode entry control or trim or test data input.

The present invention provides an output buffer including a first transistor, a second transistor and a pad-tracking circuit is disclosed. The first transistor is coupled between a supply voltage and an output node, wherein the output node is coupled to a pad. The second transistor is coupled between the output node and a reference voltage. The pad-tracking circuit is coupled to the control circuit and the first transistor, and is configured to generate a gate control signal to a gate electrode of the first transistor. The output buffer is selectively operated in an input mode and a fail-safe mode, and when the output buffer switches between the input mode and the fail-safe mode and the supply voltage of the first transistor ramps up or ramps down, the pad-tracking circuit generates the gate control signal to the gate electrode of the first transistor according to the voltage of the pad.

A semiconductor device according to an aspect of the present disclosure includes: a plurality of line layers; a first line; and a second line that is not connected to the first line and is redundantly provided to transfer a signal having a level same as a level of a signal transferred through the first line. The first line and the second line are included in different layers out of the plurality of line layers, and a distance between the first line and the second line is longer than an interlayer distance between line layers next to each other out of the plurality of line layers.

A semiconductor device includes: a first line; a second line that is not connected to the first line and is provided to transfer a signal having a level same as a level of a signal transferred through the first line; and another line different from the first line and the second line. In a line layer, a distance between the first line and the second line is longer than a distance between the first line and the other line, and is longer than a distance between the second line and the other line.

The invention relates to a safety-related switching device (10) which is equipped with an electromagnetic coil (12), a control unit (20) and a first switching means (22). The first switching means (22) is designed to activate and deactivate the electromagnetic coil (12). Moreover, the first switching means (22) is designed to receive a coil control signal (24), a monitoring signal (32) and a first higher-level control signal (26). The safety-related switching device (10) also has a receiver unit (40) for receiving an external control signal (29). The receiver unit (40) is designed to generate the first higher-level control signal (26) and a second higher-level control signal (28) from the external control signal (29). The control unit (20) is designed to receive the second higher-level control signal (28).

According to an embodiment of the present disclosure, a semiconductor memory device includes a mode register circuit including a plurality of write mode register sets for providing a plurality of setting codes or a plurality of monitoring codes; and a defect detection circuit suitable for outputting a defect determination signal by detecting any defect in the mode register circuit, based on the plurality of monitoring codes, wherein each of the write mode register sets includes: a storing circuit suitable for storing an operational code according to a mode register write command; and an output control circuit suitable for outputting the stored operational code in the storing circuit as a corresponding setting code, or inverting the stored operational code in the storing circuit to output a corresponding monitoring code, according to a test mode signal.

An item of electrical equipment has a preprocessing device for digital measured values. The preprocessing device has an integrated circuit and an electronic memory chip that contains a configuration of a logic circuit. If a fault of the preprocessing device is identified, an operation of the preprocessing device is interrupted until the configuration of the logic circuit has been loaded from a configuration memory chip into the electronic memory chip. There is also described a method for rectifying device faults, such as by reloading a configuration of a logic circuit into an electronic memory chip of a preprocessing device.

A method for protecting a reconfigurable digital integrated circuit includes multiple parallel processing channels each comprising an instance of a functional logic block and an error detection unit, the method comprising the successive steps of: activating the error detection unit in order to detect an error in at least one processing channel, executing the data replay mechanism, and then activating the error detection unit in order to detect an error in at least one processing channel, if an error is detected again, executing a self-test on each processing channel, for each processing channel, if the self-test does not detect any error, executing the data replay mechanism for this processing channel, if the self-test detects an error, reconfiguring that part of the configuration memory associated with this processing channel.

Microelectronic circuit com-prises a plurality of logic units and register circuits, arranged into a plu-rality of processing paths, and a plu-rality of monitoring units associated with respective ones of said processing paths. Each of said monitoring units is configured to produce an observation signal as a response to anomalous opera-tion of the respective processing path. Each of said plurality of logic units belongs to one of a plurality of delay classes according to an amount of delay that it is likely to generate. Said de-lay classes comprise first, second, and third classes, of which the first class covers logic units that are likely to generate longest delays, the second class covers logic units that are likely to generate shorter delays than said first class, and the third class covers logic units that are likely to generate shorter delays than said second class. At least some of said plurality of pro-cessing paths comprise logic units be-longing to said second class but are without monitoring units. At least some of said plurality of processing paths comprise logic units belonging to said third class but have monitoring units associated with them.

An electronic device includes a driver that is connected with a pin, receives an input signal, and outputs an output signal to the pin in response to the input signal, a core circuit that transfers the input signal to the driver, and a monitor circuit that receives the input and output signals and detects a stuck voltage state of the output signal based on the input and output signals. The monitor circuit includes a first detection circuit that detects the stuck voltage state when the input and output signals are logically incorrect, a second detection circuit that detects the stuck voltage state when the input and output signals are logically correct and when the output signal is at a low level, and a third detection circuit that detects the stuck voltage state when the input and output signals are logically correct and when the output signal is at a high level.