Fault detection circuitry and a corresponding method are disclosed. A count value that is indicative of the switching period of a PWM signal is determined and it is determined whether this count value is between a first threshold and a second threshold. An error signal is generated when the switching period is not between the first and the second threshold. A count value that is indicative of the switch-on duration of the PWM signal is determined and compared with a switch-on threshold in order to determine whether the switch-on duration is greater than a maximum switch-on duration. A count value that is indicative of the switch-off duration of the PWM signal is determined and compared with a switch-off threshold in order to determine whether the switch-off duration is greater than a maximum switch-off duration. Error signals can be generated when the durations are greater than the maximum durations.

Fault detection circuitry and a corresponding method are disclosed. A count value that is indicative of the switching period of a PWM signal is determined and it is determined whether this count value is between a first threshold and a second threshold. An error signal is generated when the switching period is not between the first and the second threshold. A count value that is indicative of the switch-on duration of the PWM signal is determined and compared with a switch-on threshold in order to determine whether the switch-on duration is greater than a maximum switch-on duration. A count value that is indicative of the switch-off duration of the PWM signal is determined and compared with a switch-off threshold in order to determine whether the switch-off duration is greater than a maximum switch-off duration. Error signals can be generated when the durations are greater than the maximum durations.

An apparatus includes an integrated circuit and a plurality of conducting wires disposed on the integrated circuit. The integrated circuit includes: (i) a signal generation circuit, which is configured to generate random signal and selection signal based on random or pseudo-random numbers, (ii) a transmitting circuit configured to select at least one from among the plurality of conducting wires based on the selection signal and to output the random signal through the at least one conducting wire, and (iii) a receiving circuit configured to detect an invasive attack on the integrated circuit based on signal received through the at least one conducting wire.

An integrated circuit (IC) includes a first interface configured for operation with a plurality of tenants implemented concurrently in the integrated circuit, wherein the plurality of tenants communicate with a host data processing system using the first interface. The IC includes a second interface configured for operation with the plurality of tenants, wherein the plurality of tenants communicate with one or more network nodes via a network using the second interface. The IC can include a programmable logic circuitry configured for operation with the plurality of tenants, wherein the programmable logic circuitry implements one or more hardware accelerated functions for the plurality of tenants and routes data between the first interface and the second interface. The first interface, the second interface, and the programmable logic circuitry are configured to provide isolation among the plurality of tenants.

Various implementations described herein are related to a device having an output pad that is configured to supply an output pad voltage. The device may include tracking circuitry that is configured to receive a first voltage, receive a second voltage that is different than the first voltage, receive the output pad voltage as a feedback voltage, and provide a first tracking voltage and a second tracking voltage based on the first voltage, the second voltage and the feedback voltage. The device may include output circuitry that is configured to receive the first tracking voltage and the second tracking voltage from the tracking circuitry and provide the output pad voltage to the output pad based on the first tracking voltage and the second tracking voltage.

The present invention relates to differential receivers, and more particularly to a fail-safe circuit for low-voltage differential signaling (LVDS) receivers having single differential input disconnect detection with a latchable control signal interrupt capability. In operation, the receiver output is applied to a Vout output as long as the control signal is in a normal operating state, and on the first occurrence of a fault condition trigger is applied to the input of a latch, the latch latches applying a fault state to the control signal which causes the Vout output to follow the control signal blocking the receiver output until the latch is reset after the fault has been corrected.

The present invention relates to differential receivers, and more particularly to a fail-safe circuit for low-voltage differential signaling (LVDS) receivers having single differential input disconnect detection with a latchable control signal interrupt capability. In operation, the receiver output is applied to a Vout output as long as the control signal is in a normal operating state, and on the first occurrence of a fault condition trigger is applied to the input of a latch, the latch latches applying a fault state to the control signal which causes the Vout output to follow the control signal blocking the receiver output until the latch is reset after the fault has been corrected.

Methods, systems, and apparatus for detecting single event effects. The system includes a first-modulus digital logic unit and a second-modulus digital logic unit each configured to reduce one or more operands by a respective modulus, apply an arithmetic compute logic to the reduced operands to produce a respective compute output, and reduce the respective compute output by their respective modulus. The system includes a kernel digital logic unit configured to apply the arithmetic compute logic to the operands to produce a kernel compute output, output the kernel compute output reduced by the first modulus, and output the kernel compute output reduced by the second modulus. The system includes a detector configured to detect a single event effect based on the reduced first compute output, the kernel compute output reduced by the first modulus, the reduced second compute output, and the kernel compute output reduced by the second modulus.

An active power blocking circuit in series with a squib. The active power blocking circuit may include a logic circuit, a first switch, a second switch, and an amplifier. The first switch may have a first side connected to a positive connection and a second side connected to a negative connection. The second switch may have a first side connected to the positive connection and a second side connected to the negative connection through a diode. The amplifier may be connected the second side of the second switch and the output of the amplifier may be connected to the logic circuit.

A digital value obtained from a preceding circuit element is temporarily stored and made available for a subsequent circuit element at a controlled moment of time. The digital value is received through a data input. A triggering signal is also received, a triggering edge of which defines an allowable time limit before which a digital value must be available at said data input to become available for said subsequent circuit element. Between first and second pulse-enabled subregister stages, an internal digital value from the first pulse-enabled subregister stage and information of the changing moment of said digital value at the data input in relation to said allowable time limit are used to ensure passing a valid internal digital value to the second pulse-enabled subregister stage. Said second pulse-enabled subregister stage makes said valid internal digital value available for said subsequent circuit element. A timing event observation signal is output as an indicator of said digital value at said data input having changed within a time window that begins at said allowable time limit and is shorter than one cycle of said triggering signal.