Disclosed herein is an electronic device including an IO node, with a receiver coupled to receive input from the IO node. A transmitter driver has a first n-channel DMOS with a source coupled to the IO node. A pass gate circuit decouples the IO node from the receiver based upon presence of a negative voltage at the IO node and couples the IO node to the receiver based upon lack of presence of the negative voltage at the IO node. A transmit protection circuit applies the negative voltage from the IO node to the gate and bulk of the first n-channel DMOS based upon the presence of the negative voltage at the IO node.

A supply-less transmitter output termination resistor with high accuracy is presented. This termination resistor can be used for applications with high supply voltage and low voltage devices. The termination resistor is programmable and includes many parallel branches. Each branch can be turned off or on with a switch. The biasing for the switch is in such a way that it keeps the resistance of the switch constant independent of the supply voltage or the output common mode voltage. This will increase the accuracy of the termination resistor. Besides HDMI this technique can be used for many other applications.

Described are on-die termination (ODT) systems and methods that facilitate high-speed communication between a driver die and a receiver die interconnected via one or more signal transmission lines. An ODT control system in accordance with one embodiment calibrates and maintains termination resistances and drive currents to produce optimal output swing voltages. Comparison circuitry employed to calibrate the reference resistance is also used to calibrate the drive current. Termination elements in some embodiments are divided into two adjustable resistive portions, both of which are designed to minimize capacitive loading. One portion is optimized to produce a relatively high range of adjustment, while the other is optimized for fine-tuning and glitch-free switching.

Described are on-die termination (ODT) systems and methods that facilitate high-speed communication between a driver die and a receiver die interconnected via one or more signal transmission lines. An ODT control system in accordance with one embodiment calibrates and maintains termination resistances and drive currents to produce optimal output swing voltages. Comparison circuitry employed to calibrate the reference resistance is also used to calibrate the drive current. Termination elements in some embodiments are divided into two adjustable resistive portions, both of which are designed to minimize capacitive loading. One portion is optimized to produce a relatively high range of adjustment, while the other is optimized for fine-tuning and glitch-free switching.

The output driving circuit include a pull-down driver, an input/output (IO) control logic, a gate control logic, and an inverter. The pull-down driver includes first, second, and third transistors that are sequentially coupled between a pad and a ground node. The IO control logic is configured to receive a clock signal and an enable signal, and transfer a first control signal to the third transistor. The gate control logic is configured to receive a voltage of the pad and output a feedback voltage to a gate electrode of the first transistor. The inverter is configured to invert the enable signal and transfer an inverted enable signal to the gate control logic. Therefore, the reliability of the output driving circuit can be improved.

Systems and methods according to one or more embodiments are provided for a hum reduction circuit implemented to provide a ground path between an audio generating device and a powered headset. In one example, a system includes a jack configured to accept a plug comprising a first electrical ground connection. The system also includes a switch coupled to the jack at a first end and coupled to second electrical ground connection at a second end. The system also includes the switch is configured to couple to the first electrical ground at the first end. The system further includes a bias control signal coupled to the switch, configured to control a switch bias, where a first switch bias electrically couples the first electrical ground to the second electrical ground, and a second switch bias electrically decouples the first electrical ground from the second electrical ground.

An apparatus and a method are provided for generating and transmitting one or more band segmented bootstrap signals. For example, a transmitter may be configured to generate a plurality of sequence numbers and apply cyclic shift to each of the plurality of sequence number. The transmitter is further configured to map each of the shifted sequence numbers to at least one frequency domain subcarrier of a plurality of frequency domain subcarriers, and translate each subcarrier of the plurality of subcarriers to a time domain sequence. Each subcarrier of the plurality of subcarriers may be shifted with respect to other subcarriers of the plurality of subcarriers, thereby aligning each segment of the band segmented bootstrap signals next to each other in the frequency domain.

An apparatus and a method are provided for generating and transmitting one or more band segmented bootstrap signals. For example, a transmitter may be configured to generate a plurality of sequence numbers and apply cyclic shift to each of the plurality of sequence number. The transmitter is further configured to map each of the shifted sequence numbers to at least one frequency domain subcarrier of a plurality of frequency domain subcarriers, and translate each subcarrier of the plurality of subcarriers to a time domain sequence. Each subcarrier of the plurality of subcarriers may be shifted with respect to other subcarriers of the plurality of subcarriers, thereby aligning each segment of the band segmented bootstrap signals next to each other in the frequency domain.

A transmission buffer of a signal transmission device according to the embodiment includes: a differential circuit portion that is connected between the first potential and the second potential; a variable current source portion that supplies current to the differential circuit portion; a switch port that switches between a conductive state and a disconnected state between the first transmission terminal and the fixed potential and between the second transmission terminal and the fixed potential; and a controller that controls the current supplied by the variable current source portion to the differential circuit portion, and that controls the operation of the switch portion.

A level shift circuit includes first to fourth n-type transistors, first and second p-type transistors, and first and second inverters. The first n-type transistor receives an input signal at its gate and has a drain connected to an inverted output node. The first p-type transistor is placed between a third power supply and the inverted output node. The second n-type transistor receives an inverted input signal at its gate and has a drain connected to an output node. The second p-type transistor is placed between the third power supply and the output node. The third n-type transistor is between the inverted output node and an inverted input node, and the first inverter between the drain and gate of the third n-type transistor. The fourth n-type transistor is between the output node and an input node, and the second inverter between the drain and gate of the fourth n-type transistor.