Systems, methods, and apparatus for biasing a high speed and high voltage driver using only low voltage transistors are described. The apparatus and method are adapted to control biasing voltages to the low voltage transistors such as not to exceed operating voltages of the low voltage transistors while allowing for DC to high speed operation of the driver at high voltage. A stackable and modular architecture of the driver and biasing stages is provided which can grow with a higher voltage requirement of the driver. Capacitive voltage division is used for high speed bias voltage regulation during transient phases of the driver, and resistive voltage division is used to provide bias voltage at steady state. A simpler open-drain configuration is also presented which can be used in pull-up or pull-down modes.

A drive circuit includes: an input stage configured to receive a first input signal and a second input signal, and to output a first output signal and a common-mode output signal, where the first input signal and the second input signal are complementary signals; an output stage configured to receive the first output signal, and to output a second output signal; and a duty cycle adjusting subcircuit configured to determine the first output signal and the common-mode output signal or a signal obtained by inverting the common-mode output signal as a control signal, and to adjust a duty cycle of the second output signal. The drive circuit determines the common-mode output signal or the signal obtained by inverting the common-mode output signal as the control signal of the duty cycle adjusting subcircuit, and adjusts the duty cycle of the second output signal to tend to a preset value.

A drive circuit includes: an input stage configured to receive a first input signal and a second input signal, and to output a first output signal and a common-mode output signal, where the first input signal and the second input signal are complementary signals; an output stage configured to receive the first output signal, and to output a second output signal; and a duty cycle adjusting subcircuit configured to determine the first output signal and the common-mode output signal or a signal obtained by inverting the common-mode output signal as a control signal, and to adjust a duty cycle of the second output signal. The drive circuit determines the common-mode output signal or the signal obtained by inverting the common-mode output signal as the control signal of the duty cycle adjusting subcircuit, and adjusts the duty cycle of the second output signal to tend to a preset value.

Described are on-die termination (ODT) systems and methods that facilitate high-speed communication between a driver die and a receiver die interconnected via one or more signal transmission lines. An ODT control system in accordance with one embodiment calibrates and maintains termination resistances and drive currents to produce optimal output swing voltages. Comparison circuitry employed to calibrate the reference resistance is also used to calibrate the drive current. Termination elements in some embodiments are divided into two adjustable resistive portions, both of which are designed to minimize capacitive loading. One portion is optimized to produce a relatively high range of adjustment, while the other is optimized for fine-tuning and glitch-free switching.

Described are on-die termination (ODT) systems and methods that facilitate high-speed communication between a driver die and a receiver die interconnected via one or more signal transmission lines. An ODT control system in accordance with one embodiment calibrates and maintains termination resistances and drive currents to produce optimal output swing voltages. Comparison circuitry employed to calibrate the reference resistance is also used to calibrate the drive current. Termination elements in some embodiments are divided into two adjustable resistive portions, both of which are designed to minimize capacitive loading. One portion is optimized to produce a relatively high range of adjustment, while the other is optimized for fine-tuning and glitch-free switching.

Apparatuses and methods are provided for generating, transmitting, receiving, and decoding one or more band segmented bootstrap signals and one or more corresponding partitioned post bootstrap signals. For example, a transmitter is configured to generate a first set of symbols and a second set of symbols, where the first set of symbols includes information about the second set of symbols. The transmitter is further configured to generate a third set of symbols and a fourth set of symbols, where the third set of symbols includes information about the fourth set of symbols. The transmitter is also configured to generate a data frame including the first, second, third, and fourth set of symbols. A bandwidth of the data frame includes a first segment and a second segment.

Apparatuses and methods are provided for generating, transmitting, receiving, and decoding one or more band segmented bootstrap signals and one or more corresponding partitioned post bootstrap signals. For example, a transmitter is configured to generate a first set of symbols and a second set of symbols, where the first set of symbols includes information about the second set of symbols. The transmitter is further configured to generate a third set of symbols and a fourth set of symbols, where the third set of symbols includes information about the fourth set of symbols. The transmitter is also configured to generate a data frame including the first, second, third, and fourth set of symbols. A bandwidth of the data frame includes a first segment and a second segment.

An apparatus is provided which comprises a clock inverter having an input coupled to a clock node, the clock inverter having an output, wherein the clock inverter has an N-well which is coupled to a first power supply; and a plurality of sequential logics coupled to the output of the clock inverter and also coupled to the clock node, wherein at least one sequential logics of the plurality of the sequential logics has an N-well which is coupled to a second power supply, wherein the second power supply has a voltage level lower than a voltage level of the first power supply.

A scannable data synchronizer including an input circuit, first and second pass gates, first and second inverters, and a gate controller. The input circuit drives the data nodes to opposite logic states in response to an asynchronous input data signal in a normal mode and in response to scan data in a scan test mode. Each pass gate is coupled between one of the data nodes and a corresponding one of the capture nodes, and each has at least one control terminal. The inverters are cross-coupled between the second capture nodes. The gate controller can keep the pass gates at least partially open during a metastable condition of the capture nodes, and can close the pass gates when both capture nodes stabilize to opposite logic states. In the scan test mode, the scan data is used to test the latch or register functions of the scannable data synchronizer.

A method for optimizing an implementation of a logic circuit, comprising steps of providing an interpretation of the logic circuit in terms of 3 Boolean variable majority operators M, with each of the majority operators being a function of a plurality of variables that returns a logic value assumed by more than half of the plurality of variables, and a single Boolean variable complementation operator . The method further comprises providing a commutativity, a majority (.M), an associativity (.A), a distributivity (.D), an inverter propagation (.I), a relevance (.R), a complementary associativity (.C), and a substitution (.S) transformation; and combining the .M, .C, .A, .D, .I, .R, .C and .S transformations to reduce an area of the logic circuit via (i) a reshaping procedure consisting of the .A, .C, .D, .I, .R, .S and .C transformations, applied either left-to-right or right-to-left moving identical or complemented variables in neighbor locations of the logic circuit, (ii) an elimination procedure consisting of the .M transformation, applied left-to-right, and the .D transformation, applied right-to-left, that simplify redundant operators, or (iii) an iteration of steps (i) and (ii) till a reduction in area is achieved.