An integrated circuit having programmable logic fabric, as well as system and method for computer aided design using such integrated circuit, are disclosed. This integrated circuit includes: a configurable bypassable flip-flop circuit configured to transfer information from programmable internal routing to an input bus of a programmable logic circuit; a loopback branch connected to the input bus to bypass the programmable logic circuit; and a multiplexer having a first input port connected to the loopback branch, a second input port connected to an output bus of the programmable logic circuit, and an output port connected to routing switches of the programmable internal routing. The multiplexer is configured to electrically couple either the first input port or the second input port to the output port.

A low-voltage differential signaling receiver is provided that amplifies a differential input voltage to produce a differential output voltage. A signal distortion circuit that detects a distortion in a differential output voltage to assert a signal detection signal that adjusts a gate voltage of a pair of load transistors to reduce the distortion. The load transistors are selectively diode connected to reduce power consumption.

A low-voltage differential signaling receiver is provided that amplifies a differential input voltage to produce a differential output voltage. A signal distortion circuit that detects a distortion in a differential output voltage to assert a signal detection signal that adjusts a gate voltage of a pair of load transistors to reduce the distortion. The load transistors are selectively diode connected to reduce power consumption.

A driving output circuit, a chip, and a driving output method are provided; the driving output circuit includes: a timer for outputting a timing signal; a bootstrap module for generating a first turn-on voltage based on an input signal; a charge pump for generating a second turn-on voltage based on the timing signal; a driving module including an upper driving MOSFET and a lower driving MOSFET connected to the upper driving MOSFET, and the upper driving MOSFET is connected to the lower driving MOSFET at a signal output; the first turn-on voltage and the second turn-on voltage are both used to turn on the upper driving MOSFET and/or the lower driving MOSFET to cause the signal output to output an output signal. The present disclosure provides a dynamic hybrid driving output circuit, which has improved gate oxide reliability and an enhanced anti-leakage function when not powered.

Described are on-die termination (ODT) systems and methods that facilitate high-speed communication between a driver die and a receiver die interconnected via one or more signal transmission lines. An ODT control system in accordance with one embodiment calibrates and maintains termination resistances and drive currents to produce optimal output swing voltages. Comparison circuitry employed to calibrate the reference resistance is also used to calibrate the drive current. Termination elements in some embodiments are divided into two adjustable resistive portions, both of which are designed to minimize capacitive loading. One portion is optimized to produce a relatively high range of adjustment, while the other is optimized for fine-tuning and glitch-free switching.

Described are on-die termination (ODT) systems and methods that facilitate high-speed communication between a driver die and a receiver die interconnected via one or more signal transmission lines. An ODT control system in accordance with one embodiment calibrates and maintains termination resistances and drive currents to produce optimal output swing voltages. Comparison circuitry employed to calibrate the reference resistance is also used to calibrate the drive current. Termination elements in some embodiments are divided into two adjustable resistive portions, both of which are designed to minimize capacitive loading. One portion is optimized to produce a relatively high range of adjustment, while the other is optimized for fine-tuning and glitch-free switching.

The present disclosure relates to a structure including a level shifter circuit which receives an input signal and at least one voltage reference signal and outputs at least one level shifted output signal, a pre-driver circuit which receives the at least one level shifted output signal and outputs at least one pre-driver output signal, the pre-driver circuit including at least one delay circuit, and a main driver circuit which receives the at least one pre-driver output signal and outputs a main driver output signal.

Systems, apparatuses, and methods for implementing a combo scheme for direct current (DC) level shifting of signals are disclosed. A receiver circuit receives an input signal on a first interface. The first interface is coupled to a resistor in parallel with a capacitor which passes the input signal to a second interface. Also, the first interface is coupled to a first pair of current sources between ground and a voltage source, and the second interface is coupled to a second pair of current sources between ground and the voltage source. An op-amp drives the current sources based on a difference between a sensed common mode voltage and a reference voltage. Based on this circuit configuration, the receiver circuit is able to prevent baseline wander, perform a DC level shift of the input signal, and achieve linear equalization of the input signal.

Systems, methods, and apparatus for biasing a high speed and high voltage driver using only low voltage transistors are described. The apparatus and method are adapted to control biasing voltages to the low voltage transistors such as not to exceed operating voltages of the low voltage transistors while allowing for DC to high speed operation of the driver at high voltage. A stackable and modular architecture of the driver and biasing stages is provided which can grow with a higher voltage requirement of the driver. Capacitive voltage division is used for high speed bias voltage regulation during transient phases of the driver, and resistive voltage division is used to provide bias voltage at steady state. A simpler open-drain configuration is also presented which can be used in pull-up or pull-down modes.

A bootstrapped switch includes a first transistor, a second transistor, a first capacitor, three switches, and a switch circuit. The switch circuit includes a first switch, a second switch, a third switch, a fourth switch, a fifth switch, a sixth switch, and a second capacitor. The first transistor receives the input voltage and outputs the output voltage. The first terminal of the second transistor receives the input voltage, and the second terminal of the second transistor is coupled to the first capacitor. The control terminal of the first switch receives a clock. The second switch is coupled between the control terminal of the first transistor and the first switch. The second capacitor is coupled to a reference voltage through the third switch and the sixth switch, coupled to the input voltage through the fifth switch, and coupled to the control terminal of the first transistor through the fourth switch.