Embodiments include a logic gate system comprising a first micro-cantilever beam arranged in parallel to a second micro-cantilever beam in which a length of the first micro-cantilever beam is shorter than a length of the second micro-cantilever beam. The first micro-cantilever beam is adjacent to the second micro-cantilever beam and the first micro-cantilever beam is coupled to an input DC bias voltage source to the logic gate system. The second micro-cantilever beam is coupled to an input AC voltage signal that dynamically sets a logic operation of the logic gate system by at least changing an operating resonance frequency for one or more of the first micro-cantilever beam and the second micro-cantilever beam.

Embodiments include a logic gate system comprising a first micro-cantilever beam arranged in parallel to a second micro-cantilever beam in which a length of the first micro-cantilever beam is shorter than a length of the second micro-cantilever beam. The first micro-cantilever beam is adjacent to the second micro-cantilever beam and the first micro-cantilever beam is coupled to an input DC bias voltage source to the logic gate system. The second micro-cantilever beam is coupled to an input AC voltage signal that dynamically sets a logic operation of the logic gate system by at least changing an operating resonance frequency for one or more of the first micro-cantilever beam and the second micro-cantilever beam.

A memory includes an error detection circuit that identifies a faulty feature in an array of memory cells within the memory. A redundancy enable circuit functions to replace the faulty feature with a redundant feature. The error detection circuit and the redundancy enable circuit function concurrently with a read operation on the array of memory cells.

An integrated circuit designing system includes a non-transitory storage medium encoded with a first set of standard cell layouts and a second set of standard cell layouts both being configured to perform a predetermined function. The predetermined manufacturing process having a nominal minimum pitch (T) of metal lines. Each standard cell layout of the first set of standard cell layouts and the second set of standard cell layouts having a cell height (H) wherein the cell height is a non-integral multiple of the nominal minimum pitch. A hardware processor communicatively is coupled with the non-transitory storage medium and is configured to execute a set of instructions for generating an integrated circuit layout based on the first set of standard cell layouts, the second set of standard cell layouts and the nominal minimum pitch; and creating a data file corresponding to the integrated circuit layout.

An integrated circuit designing system includes a non-transitory storage medium encoded with a first set of standard cell layouts and a second set of standard cell layouts both being configured to perform a predetermined function. The predetermined manufacturing process having a nominal minimum pitch (T) of metal lines. Each standard cell layout of the first set of standard cell layouts and the second set of standard cell layouts having a cell height (H) wherein the cell height is a non-integral multiple of the nominal minimum pitch. A hardware processor communicatively is coupled with the non-transitory storage medium and is configured to execute a set of instructions for generating an integrated circuit layout based on the first set of standard cell layouts, the second set of standard cell layouts and the nominal minimum pitch; and creating a data file corresponding to the integrated circuit layout.

A high speed signal drive circuit includes a D-PHY drive signal generation module, a C-PHY drive signal generation module, a drive signal selection module and a multiplex drive module. An output terminal of the D-PHY drive signal generation module and an output terminal of the C-PHY drive signal generation module are both connected to an input terminal of the drive signal selection module. An output terminal of the drive signal selection module is connected to an input terminal of the multiplex drive module. The drive signal selection module controls control switches of the multiplex drive module to be on and off based on a D-PHY drive signal or a C-PHY drive signal, so that the multiplex drive module functions as a D-PHY drive circuit or a C-PHY drive circuit. Thus, dual functions of the D-PHY drive circuit and the C-PHY drive circuit can be realized.

A high speed signal drive circuit includes a D-PHY drive signal generation module, a C-PHY drive signal generation module, a drive signal selection module and a multiplex drive module. An output terminal of the D-PHY drive signal generation module and an output terminal of the C-PHY drive signal generation module are both connected to an input terminal of the drive signal selection module. An output terminal of the drive signal selection module is connected to an input terminal of the multiplex drive module. The drive signal selection module controls control switches of the multiplex drive module to be on and off based on a D-PHY drive signal or a C-PHY drive signal, so that the multiplex drive module functions as a D-PHY drive circuit or a C-PHY drive circuit. Thus, dual functions of the D-PHY drive circuit and the C-PHY drive circuit can be realized.

The present disclosure is directed to various mechanical logic gates. In one example a mechanical logic NOT gate system is formed which has a first pair of bi-stable buckling structures each being operatively connected at a first connection point thereof to one another, and also to a first rigid structure at second connection points, the first rigid structure being held stationary. A second pair of bi-stable buckling flexures is each operatively connected at first connection points thereof to each other and at second connection points thereof to a second rigid structure being held stationary. An output element is coupled a first one of each of the first and second pairs of bi-stable buckling structures. An input element is coupled to a second one of each of the first and second pairs of bi-stable buckling structures. The output element moves from a logic 1 position to a logic 0 position in response to movement of the input element from a logic 0 position to a logic 1 positions, respectively.

The present disclosure is directed to various mechanical logic gates. In one example a mechanical logic NOT gate system is formed which has a first pair of bi-stable buckling structures each being operatively connected at a first connection point thereof to one another, and also to a first rigid structure at second connection points, the first rigid structure being held stationary. A second pair of bi-stable buckling flexures is each operatively connected at first connection points thereof to each other and at second connection points thereof to a second rigid structure being held stationary. An output element is coupled a first one of each of the first and second pairs of bi-stable buckling structures. An input element is coupled to a second one of each of the first and second pairs of bi-stable buckling structures. The output element moves from a logic 1 position to a logic 0 position in response to movement of the input element from a logic 0 position to a logic 1 positions, respectively.

The present disclosure is directed to various mechanical logic gates. In one example a mechanical logic NOT gate system is formed which has a first pair of bi-stable buckling structures each being operatively connected at a first connection point thereof to one another, and also to a first rigid structure at second connection points, the first rigid structure being held stationary. A second pair of bi-stable buckling flexures is each operatively connected at first connection points thereof to each other and at second connection points thereof to a second rigid structure being held stationary. An output element is coupled a first one of each of the first and second pairs of bi-stable buckling structures. An input element is coupled to a second one of each of the first and second pairs of bi-stable buckling structures. The output element moves from a logic 1 position to a logic 0 position in response to movement of the input element from a logic 0 position to a logic 1 positions, respectively.