The present disclosure is directed to various mechanical logic gates. In one example a mechanical logic NOT gate system is formed which has a first pair of bi-stable buckling structures each being operatively connected at a first connection point thereof to one another, and also to a first rigid structure at second connection points, the first rigid structure being held stationary. A second pair of bi-stable buckling flexures is each operatively connected at first connection points thereof to each other and at second connection points thereof to a second rigid structure being held stationary. An output element is coupled a first one of each of the first and second pairs of bi-stable buckling structures. An input element is coupled to a second one of each of the first and second pairs of bi-stable buckling structures. The output element moves from a logic 1 position to a logic 0 position in response to movement of the input element from a logic 0 position to a logic 1 positions, respectively.

A computer program product, including a non-transitory, computer-readable medium containing instructions therein which, when executed by at least one processor, cause the at least one processor to perform a performance analysis of a network of interconnected nodes, the nodes configured to perform corresponding logic functions. The performance analysis includes, for a pipeline node in the network, calculating a pre-charging finish time of the pipeline node based on an evaluation finish time of a fanout node of the pipeline node and an acknowledge output time parameter of the fanout node. The performance analysis further includes, for the pipeline node in the network, calculating a cycle time of the pipeline node based on the calculated pre-charging finish time and an evaluation finish time of a fanin node of the pipeline node.

An electronic device includes a die stack having a plurality of die. The die stack includes a die parity path spanning the plurality of die and configured to alternatingly identify each die as a first type or a second type. The die stack further includes an inter-die signal path spanning the plurality of die and configured to propagate an inter-die signal through the plurality of die, wherein the inter-die signal path is configured to invert a logic state of the inter-die signal between each die. Each die of the plurality of die includes signal formatting logic configured to selectively invert a logic state of the inter-die signal before providing it to other circuitry of the die responsive to whether the die is designated as the first type or the second type.

A logic cell including a fixed assembly including a first electrode, a mobile assembly including a second electrode, and third, fourth, and fifth electrodes, wherein: the first, second, third, fourth, and fifth electrodes are insulated from one another; the first and second electrodes define a capacitor variable according to the position of the mobile assembly relative to the fixed assembly; the third electrode is connected to a node of application of a first logic input signal; the fourth electrode is connected to a node of application of a second logic input signal; the fifth electrode is connected to a reference node; and the position of the second electrode relative to the first electrode is a function of a combination of the first and second logic input signals.

A logic cell including a fixed assembly including a first electrode, a mobile assembly including a second electrode, and third, fourth, and fifth electrodes, wherein: the first, second, third, fourth, and fifth electrodes are insulated from one another; the first and second electrodes define a capacitor variable according to the position of the mobile assembly relative to the fixed assembly; the third electrode is connected to a node of application of a first logic input signal; the fourth electrode is connected to a node of application of a second logic input signal; the fifth electrode is connected to a reference node; and the position of the second electrode relative to the first electrode is a function of a combination of the first and second logic input signals.

A mechanical resonator-based cascadable logic device includes which includes a resonator having a beam with a first fixed end, a second fixed end, and a length between the first and second fixed ends. A first electrode and a second electrode are aligned along a first side of the beam. A third electrode and a fourth electrode are aligned along a second side of the beam and opposite the first and second electrodes. A DC voltage source is coupled to one of the first and second fixed ends of the beam. At least one of the first, second, third, and fourth electrodes is coupled to a first AC voltage source so that a logic operation is performed by activating a second resonant mode of the resonator.

A mechanical resonator-based cascadable logic device includes which includes a resonator having a beam with a first fixed end, a second fixed end, and a length between the first and second fixed ends. A first electrode and a second electrode are aligned along a first side of the beam. A third electrode and a fourth electrode are aligned along a second side of the beam and opposite the first and second electrodes. A DC voltage source is coupled to one of the first and second fixed ends of the beam. At least one of the first, second, third, and fourth electrodes is coupled to a first AC voltage source so that a logic operation is performed by activating a second resonant mode of the resonator.

A system comprises at least one processor configured to perform technology mapping to map logic elements in a logic netlist to corresponding dual-rail modules in a library. The technology mapping results in a network of interconnected nodes and the mapped dual-rail modules are arranged at corresponding nodes of the network. The processor is configured to optimize the network and perform the technology mapping based on at least one satisfiability-don't-care condition. Performance analysis may be performed by calculating a cycle time of a pipeline node in the network based on a calculated pre-charging finish time and an evaluation finish time of a fanin node of the pipeline node.

A mechanical resonator-based cascadable logic device includes which includes a resonator having a beam with a first fixed end, a second fixed end, and a length between the first and second fixed ends. A first electrode and a second electrode are aligned along a first side of the beam. A third electrode and a fourth electrode are aligned along a second side of the beam and opposite the first and second electrodes. A DC voltage source is coupled to one of the first and second fixed ends of the beam. At least one of the first, second, third, and fourth electrodes is coupled to a first AC voltage source so that a logic operation is performed by activating a second resonant mode of the resonator.

A mechanical resonator-based cascadable logic device includes which includes a resonator having a beam with a first fixed end, a second fixed end, and a length between the first and second fixed ends. A first electrode and a second electrode are aligned along a first side of the beam. A third electrode and a fourth electrode are aligned along a second side of the beam and opposite the first and second electrodes. A DC voltage source is coupled to one of the first and second fixed ends of the beam. At least one of the first, second, third, and fourth electrodes is coupled to a first AC voltage source so that a logic operation is performed by activating a second resonant mode of the resonator.