A system-on-chip includes: a dynamic power monitor configured to generate a power detection signal by calculating an amount of power consumed by a functional circuit in real time; a frequency controller configured to detect an idle period and a running period of the functional circuit in response to the power detection signal, and generate a clock control signal based on the power detection signal; and a clock controller configured to change a frequency of a clock signal provided to the functional circuit, based on the clock control signal. The running period includes: a first running period in which the frequency of the clock signal has a first value based on the clock control signal; and a second running period in which the frequency of the clock signal has a second value that is greater than the first value based on the clock control signal.

A circuit includes a first transistor having first and second current terminals and a first control input, and a second transistor having third and fourth current terminals and a second control input. The third current terminal is connected to the second current terminal at an intermediate node and the fourth current terminal connected to a ground or supply node. In some cases, a third transistor is connected to the intermediate node to bias the intermediate rather than letting the intermediate node float. In other cases, a capacitor is connected to the intermediate node to reduce a negative voltage that might otherwise be present on the intermediate node.

A circuit includes a first transistor having first and second current terminals and a first control input, and a second transistor having third and fourth current terminals and a second control input. The third current terminal is connected to the second current terminal at an intermediate node and the fourth current terminal connected to a ground or supply node. In some cases, a third transistor is connected to the intermediate node to bias the intermediate rather than letting the intermediate node float. In other cases, a capacitor is connected to the intermediate node to reduce a negative voltage that might otherwise be present on the intermediate node.

Mechanisms can be designed to manage non-contact forces to reduce energy consumption and/or to control interactions between the parts. Management of non-contact forces is especially useful in micro-scale and nano-scale mechanisms, where van der Waals attraction between parts of the mechanism may be significant to the operation of the mechanism.

Mechanisms can be designed to manage non-contact forces to reduce energy consumption and/or to control interactions between the parts. Management of non-contact forces is especially useful in micro-scale and nano-scale mechanisms, where van der Waals attraction between parts of the mechanism may be significant to the operation of the mechanism.

Provided are a low-jitter digital isolator circuit and a digital isolator including the same. The digital isolator circuit includes a signal transmitting module, a signal receiving module, and an isolation channel connected between the signal transmitting module and the signal receiving module. The signal transmitting module is provided with a signal input terminal, and the signal receiving module is provided with a signal output terminal. The signal transmitting module includes a reset circuit, an oscillator and a transmitting circuit which are sequentially connected. The reset circuit is connected to the signal input terminal. The transmitting circuit is connected to the isolation channel. The signal receiving module includes a receiving circuit connected to the isolation channel. In the present invention, more stable signal transmission and a better isolation effect are achieved, and the area and cost of the digital isolator circuit are reduced.

Provided are a low-jitter digital isolator circuit and a digital isolator including the same. The digital isolator circuit includes a signal transmitting module, a signal receiving module, and an isolation channel connected between the signal transmitting module and the signal receiving module. The signal transmitting module is provided with a signal input terminal, and the signal receiving module is provided with a signal output terminal. The signal transmitting module includes a reset circuit, an oscillator and a transmitting circuit which are sequentially connected. The reset circuit is connected to the signal input terminal. The transmitting circuit is connected to the isolation channel. The signal receiving module includes a receiving circuit connected to the isolation channel. In the present invention, more stable signal transmission and a better isolation effect are achieved, and the area and cost of the digital isolator circuit are reduced.

A transformer includes a primary winding and a secondary winding. A transmitting circuit is coupled to a primary winding of a transformer and supplies a current signal to the primary winding with a polarity that changes in response to a change of the input signal level. A latch circuit is arranged such that its set terminal is coupled to one end of the secondary winding of the transformer, and its reset terminal is coupled to the other end of the secondary winding of the transformer. A first switch is arranged between a common voltage node at which a common voltage occurs and the set terminal. When the output of the latch circuit is high, the first switch is turned on. A second switch is arranged between the common voltage node and the reset terminal. When the output of the latch circuit is low, the second switch is turned on.

The disclosure provides an electronic device including a host control circuit, a display driving circuit, a touch driving circuit and a logic circuit. The host control circuit is configured to provide a first reset control signal. The display driving circuit is configured to reset according to the first reset control signal. The logic circuit is configured to generate a second reset control signal to the touch driving circuit according to the first reset control signal and an enable signal. During a sleep mode of the electronic device, the enable signal has a first logic level. In response to the enable signal at the first logic level, the logic circuit generates the second reset control signal at the first logic level. The touch driving circuit does not reset according to the second reset control signal at the first logic level.

The disclosure provides an electronic device including a host control circuit, a display driving circuit, a touch driving circuit and a logic circuit. The host control circuit is configured to provide a first reset control signal. The display driving circuit is configured to reset according to the first reset control signal. The logic circuit is configured to generate a second reset control signal to the touch driving circuit according to the first reset control signal and an enable signal. During a sleep mode of the electronic device, the enable signal has a first logic level. In response to the enable signal at the first logic level, the logic circuit generates the second reset control signal at the first logic level. The touch driving circuit does not reset according to the second reset control signal at the first logic level.