An apparatus includes an adjustment circuit configured to receive a pulsed-width modulation (PWM) input, generate an adjusted PWM signal based upon the PWM input, and determine that a first pulse of the PWM input is shorter than a runt signal limit. The adjustment circuit is further configured to, in the adjusted PWM signal, extend the first pulse of the PWM input based on the determination that the PWM input is shorter than the runt signal limit, and output the adjusted PWM signal to an electronic device.

A clock generator circuit including an integer divider, having a first input receiving a reference clock and configured to generate an intermediate clock at a frequency divided down from a frequency of the reference clock by an integer value, a digital delay stage configured to generate a delayed intermediate clock delayed from the intermediate clock by a number of fractional cycles of the reference clock selected responsive to a fractional cycle value, and an analog delay stage configured to generate an output clock delayed from the delayed intermediate clock by a delay value selected responsive to a fine adjustment value. The clock generator circuit further includes math engine circuitry configured to compute a phase adjustment code responsive to the phase adjustment word, the phase adjustment code comprising the integer value, the fractional cycle value, and the fine adjustment value. The clock generator circuit may be implemented in a clock domain of a system along with one or more other clock generator circuits that each generate an output clock based on a reference clock generated by a reference clock source, such as a phase-locked loop.

A clock generator circuit including an integer divider, having a first input receiving a reference clock and configured to generate an intermediate clock at a frequency divided down from a frequency of the reference clock by an integer value, a digital delay stage configured to generate a delayed intermediate clock delayed from the intermediate clock by a number of fractional cycles of the reference clock selected responsive to a fractional cycle value, and an analog delay stage configured to generate an output clock delayed from the delayed intermediate clock by a delay value selected responsive to a fine adjustment value. The clock generator circuit further includes math engine circuitry configured to compute a phase adjustment code responsive to the phase adjustment word, the phase adjustment code comprising the integer value, the fractional cycle value, and the fine adjustment value. The clock generator circuit may be implemented in a clock domain of a system along with one or more other clock generator circuits that each generate an output clock based on a reference clock generated by a reference clock source, such as a phase-locked loop.

Embodiments relate to a clock counter, a method for clock counting, and a storage apparatus. The clock counter includes a clock frequency-dividing circuit, a plurality of counting circuits, and an adding circuit. The clock frequency-dividing circuit receives a clock signal and divide a frequency of the clock signal to output a plurality of frequency-divided clock signals, sum of number of pulses of the plurality of frequency-divided clock signals being equal to number of pulses of the clock signal. The plurality of counting circuits are connected to the clock frequency-dividing circuit, each of the plurality of counting circuits being configured to respectively count pulses for each of the plurality of frequency-divided clock signals and generate an initial count value. The adding circuit is connected to the plurality of counting circuits, and adds up the initial count values of the plurality of counting circuits to generate a target count value.

An apparatus includes an adjustment circuit configured to receive a pulsed-width modulation (PWM) input, generate an adjusted PWM signal based upon the PWM input, and determine that a first pulse of the PWM input is shorter than a runt signal limit. The adjustment circuit is further configured to, in the adjusted PWM signal, extend the first pulse of the PWM input based on the determination that the PWM input is shorter than the runt signal limit, and output the adjusted PWM signal to an electronic device.

An apparatus includes an adjustment circuit configured to receive a pulsed-width modulation (PWM) input, generate an adjusted PWM signal based upon the PWM input, and determine that a first pulse of the PWM input is shorter than a runt signal limit. The adjustment circuit is further configured to, in the adjusted PWM signal, extend the first pulse of the PWM input based on the determination that the PWM input is shorter than the runt signal limit, and output the adjusted PWM signal to an electronic device.

A frequency multiplier system includes a first frequency multiplier circuit to generate a first signal having a first frequency. The first frequency multiplier circuit includes a first post-divider circuit to divide the first frequency of the first signal to a first output frequency within a bounded first range of frequencies, and a first programmable frequency transition controller to control a transitioning frequency relationship between the first signal having the first frequency and a target signal having a desired target frequency. The system includes a second frequency multiplier circuit to generate a second signal having a second frequency. The second frequency multiplier circuit includes a second post-divider circuit configured to divide the second frequency of the second signal to a second output frequency within a bounded second range of frequencies, and a second programmable frequency transition controller to control a transitioning frequency relationship between the second signal having the second frequency and the target signal having the desired target frequency. A multi-transition controller is coupled to both the first frequency multiplier circuit and the second frequency multiplier circuit to, upon a desired change from the first output frequency to the target output frequency, select one of the first output frequency or the second output frequency as a system output frequency.

A frequency multiplier system includes a first frequency multiplier circuit to generate a first signal having a first frequency. The first frequency multiplier circuit includes a first post-divider circuit to divide the first frequency of the first signal to a first output frequency within a bounded first range of frequencies, and a first programmable frequency transition controller to control a transitioning frequency relationship between the first signal having the first frequency and a target signal having a desired target frequency. The system includes a second frequency multiplier circuit to generate a second signal having a second frequency. The second frequency multiplier circuit includes a second post-divider circuit configured to divide the second frequency of the second signal to a second output frequency within a bounded second range of frequencies, and a second programmable frequency transition controller to control a transitioning frequency relationship between the second signal having the second frequency and the target signal having the desired target frequency. A multi-transition controller is coupled to both the first frequency multiplier circuit and the second frequency multiplier circuit to, upon a desired change from the first output frequency to the target output frequency, select one of the first output frequency or the second output frequency as a system output frequency.

A method and system are provided for controlling transfer switch operations in a power distribution system. The method and system involve monitoring an electrical parameter of an electrical signal from a first power source associated with supplying power to a load; determining whether the electrical parameter satisfies a parameter threshold; selecting to increment or decrement a count value in accordance with the determination; and responsive to determining that the count value satisfies a first count threshold, initiating a start signal to start operation of a second power source to supply power to the load. The electrical parameter can be voltage or frequency, or other parameter(s) from which a power quality of the electrical signal may be evaluated. The electrical signal can be a single or polyphase electrical signal.

A method and system are provided for controlling transfer switch operations in a power distribution system. The method and system involve monitoring an electrical parameter of an electrical signal from a first power source associated with supplying power to a load; determining whether the electrical parameter satisfies a parameter threshold; selecting to increment or decrement a count value in accordance with the determination; and responsive to determining that the count value satisfies a first count threshold, initiating a start signal to start operation of a second power source to supply power to the load. The electrical parameter can be voltage or frequency, or other parameter(s) from which a power quality of the electrical signal may be evaluated. The electrical signal can be a single or polyphase electrical signal.