An apparatus includes an adjustment circuit configured to receive a pulsed-width modulation (PWM) input, generate an adjusted PWM signal based upon the PWM input, and determine that a first pulse of the PWM input is shorter than a runt signal limit. The adjustment circuit is further configured to, in the adjusted PWM signal, extend the first pulse of the PWM input based on the determination that the PWM input is shorter than the runt signal limit, and output the adjusted PWM signal to an electronic device.

An apparatus includes an adjustment circuit configured to receive a pulsed-width modulation (PWM) input, generate an adjusted PWM signal based upon the PWM input, and determine that a first pulse of the PWM input is shorter than a runt signal limit. The adjustment circuit is further configured to, in the adjusted PWM signal, extend the first pulse of the PWM input based on the determination that the PWM input is shorter than the runt signal limit, and output the adjusted PWM signal to an electronic device.

Techniques are described for implementing read-out architectures to support high-speed serialized read-out of a large number of digital bit values, such as for high-resolution pixel conversions in CMOS image sensor applications. For example, outputs from a large number of digital data sources (e.g., counters) are coupled with transmission gates of the read-out architecture, and the transmission gates are sequentially enabled, thereby shifting in bit data from the data sources one at a time. The transmission gates are grouped into gate groups. For each gate group, embodiments seek balance total path delay across the gate groups by controlling clock and data path delays to be inversely related, and ensuring that total path delays for all gate groups are within a single clock period. Some embodiments include a partitioned bus for further gate group-level control over the path delay and data bus capacitance.

Techniques are described for implementing read-out architectures to support high-speed serialized read-out of a large number of digital bit values, such as for high-resolution pixel conversions in CMOS image sensor applications. For example, outputs from a large number of digital data sources (e.g., counters) are coupled with transmission gates of the read-out architecture, and the transmission gates are sequentially enabled, thereby shifting in bit data from the data sources one at a time. The transmission gates are grouped into gate groups. For each gate group, embodiments seek balance total path delay across the gate groups by controlling clock and data path delays to be inversely related, and ensuring that total path delays for all gate groups are within a single clock period. Some embodiments include a partitioned bus for further gate group-level control over the path delay and data bus capacitance.

Embodiments of the present invention relate to an architecture that uses hierarchical statistically multiplexed counters to extend counter life by orders of magnitude. Each level includes statistically multiplexed counters. The statistically multiplexed counters includes P base counters and S subcounters, wherein the S subcounters are dynamically concatenated with the P base counters. When a row overflow in a level occurs, counters in a next level above are used to extend counter life. The hierarchical statistically multiplexed counters can be used with an overflow FIFO to further extend counter life.

The present invention provides a fractional frequency divider, wherein the fractional frequency divider includes a plurality of registers, a control signal generator and a clock gating circuit. Regarding the plurality of registers, at least a portion of the registers are set to have values. The control signal generator is configured to generate a control signal based on an input clock signal and values in the at least a portion of the registers, wherein the control generator sequentially generates the control signal during each cycle of the input clock signal. The clock gating circuit is configured to refer to the control signal to mask or not mask the input clock signal to generate an output clock signal.

An apparatus of preventing ESD and EMP coupled between a signal input and a signal output is provided with a first diode of forward bias including a positive terminal and a negative terminal connected to the signal input and ground respectively; and a first diode of reverse bias including a negative terminal and a positive terminal connected to the signal input and the ground respectively. The semiconductor is a diode including a p-type semiconductor region made of semiconductor material having a predetermined band gap and an n-type semiconductor region made of semiconductor material having a predetermined band gap. The predetermined band gap is greater than 3 eV. The diode operates in forward bias to discharge current generated by ESD and/or EMP. A method of preventing ESD and EMP is also provided.

An apparatus of preventing ESD and EMP coupled between a signal input and a signal output is provided with a first diode of forward bias including a positive terminal and a negative terminal connected to the signal input and ground respectively; and a first diode of reverse bias including a negative terminal and a positive terminal connected to the signal input and the ground respectively. The semiconductor is a diode including a p-type semiconductor region made of semiconductor material having a predetermined band gap and an n-type semiconductor region made of semiconductor material having a predetermined band gap. The predetermined band gap is greater than 3 eV. The diode operates in forward bias to discharge current generated by ESD and/or EMP. A method of preventing ESD and EMP is also provided.

Counter, pixel circuit, display panel, display device are provided. The counter includes: start-up circuit generating and outputting start-up signal by clock signal; M first and M second combinational logic circuits, alternate and cascaded, where M is integer no less than 1. Input terminal of first combinational logic circuit is coupled to output terminal of start-up circuit or second combinational logic circuit of previous stage, input terminal of second combinational logic circuit is coupled to output terminal of first combinational logic circuit of previous stage. Clock signal terminals of first, second combinational logic circuits are for inputting clock signal. First combinational logic circuit is for outputting clock signal in first time period and continuously outputting low level signal in second time period. Second combinational logic circuit is for outputting inverted signal of clock signal in third time period and continuously outputting low level signal in fourth time period.

A frequency divider circuit includes: a first latch circuit that including: a pair of input transistors each having a gate thereof configured to connect to a signal line to which a first voltage is supplied; and a pair of output nodes, and configured to receive a single-phase clock signal; and a second latch circuit of SR-type, the second latch circuit having a set input thereof and a reset input thereof configured to connect to the pair of output nodes of the first latch circuit, and configured to output differential clock signals of which frequency is half a frequency of the single-phase clock signal. The first latch circuit is configured to perform amplification and reset operations alternately repeatedly in response to the single-phase clock signal.