An analog counter circuit for use with a digital pixel includes an input; an output; a first inverter connected to the input that produces on a first inverter output a time delayed inverted signal (RP*) from an input signal received at the input; a second inverter connected to the first inverter output that produces a time delayed signal (RP) at a second inverter output from the input signal and that is delayed relative to RP* and a control switch connected between a source voltage and a floating node. The control switch is controlled by the signal RP* on the first inverter output. The analog counter also includes a feedback capacitor connected between the second inverter output and the floating node; an accumulating capacitor that accumulates at least some of a charge that passes through the control switch; and an injection switch connected between the control switch and the accumulating capacitor.

An event counter circuit can be configured to monitor operation of a system where a moving average register circuit can be configured to store a moving average value updated in each cycle of operation of the system by adding a number of system events occurring during a current cycle of the system operation to either 1) a current moving average value stored in the moving average register circuit or 2) a keep value generated by partitioning the current moving average value into the keep value and a transfer value representing system events not included in a determination of the moving average value for subsequent cycles of operation of the system.

Disclosed is an integrated circuit having a trim function for an embedded analog component or digital component. The integrated circuit includes a trim value generator configured to provide a varying trim value, a measurement target selected from a digital component and an analog component and configured to provide a measured value as a result of an internal operation corresponding to the trim value, a determination unit configured to determine the measured value based on a reference value received from the outside and to provide a trim control signal when the measured value corresponds to a preset target value, and a storage configured to store a current trim value as a measured result value in response to the trim control signal.

Disclosed is an integrated circuit having a trim function for an embedded analog component or digital component. The integrated circuit includes a trim value generator configured to provide a varying trim value, a measurement target selected from a digital component and an analog component and configured to provide a measured value as a result of an internal operation corresponding to the trim value, a determination unit configured to determine the measured value based on a reference value received from the outside and to provide a trim control signal when the measured value corresponds to a preset target value, and a storage configured to store a current trim value as a measured result value in response to the trim control signal.

A clock compensation circuit includes a delay circuit configured to generate a plurality of second clock signals by delaying a plurality of first clock signals, a voltage conversion circuit configured to convert phase differences between the plurality of second clock signals into voltages and output converted voltages as a plurality of phase difference voltages, and a comparison circuit configured to generate a plurality of phase difference detection signals by comparing the plurality of phase difference voltages with a reference voltage. The clock compensation circuit also includes a phase error control circuit configured to generate a plurality of control signals for controlling the delay circuit, the voltage conversion circuit, and the comparison circuit according to any of the plurality of second clock signals and the plurality of phase difference detection signals.

A calibration circuit includes an oscillator configured to generate an oscillation signal according to a control voltage; a counter configured to generate a count value according to the oscillation signal; and a control circuit configured to control a pull-up driver and a pull-down driver commonly coupled to an output node according to the count value, wherein the control circuit compares a reference count value of the counter by providing a reference voltage as the control voltage for a unit control period with a count value of the counter by providing an output voltage of the output node as the control voltage for a unit control period, and controls a pull-up control signal that adjusts turn-on impedance of the pull-up driver and a pull-down control signal that adjusts turn-on impedance of the pull-down driver.

A calibration circuit includes an oscillator configured to generate an oscillation signal according to a control voltage; a counter configured to generate a count value according to the oscillation signal; and a control circuit configured to control a pull-up driver and a pull-down driver commonly coupled to an output node according to the count value, wherein the control circuit compares a reference count value of the counter by providing a reference voltage as the control voltage for a unit control period with a count value of the counter by providing an output voltage of the output node as the control voltage for a unit control period, and controls a pull-up control signal that adjusts turn-on impedance of the pull-up driver and a pull-down control signal that adjusts turn-on impedance of the pull-down driver.

A frequency counter circuit includes a first counter path to receive a digitally-controlled oscillator (DCO) clock signal and is configured to generate a first count corresponding to a first frequency of a first reduced clock signal corresponding to the DCO clock signal. A second counting path receives the DCO clock signal and generates a second count corresponding to a second frequency of a second reduced clock signal corresponding to the DCO clock signal. The first reduced clock signal is an integer multiple frequency of the second reduced clock signal. Detection circuitry detects a timing violation associated with the DCO clock signal based on a comparison between at least a portion of the first count and at least a portion of the second count.

A frequency counter circuit includes a first counter path to receive a digitally-controlled oscillator (DCO) clock signal and is configured to generate a first count corresponding to a first frequency of a first reduced clock signal corresponding to the DCO clock signal. A second counting path receives the DCO clock signal and generates a second count corresponding to a second frequency of a second reduced clock signal corresponding to the DCO clock signal. The first reduced clock signal is an integer multiple frequency of the second reduced clock signal. Detection circuitry detects a timing violation associated with the DCO clock signal based on a comparison between at least a portion of the first count and at least a portion of the second count.

Embodiments of the present invention relate to an architecture that uses hierarchical statistically multiplexed counters to extend counter life by orders of magnitude. Each level includes statistically multiplexed counters. The statistically multiplexed counters includes P base counters and S subcounters, wherein the S subcounters are dynamically concatenated with the P base counters. When a row overflow in a level occurs, counters in a next level above are used to extend counter life. The hierarchical statistically multiplexed counters can be used with an overflow FIFO to further extend counter life.