A circuit system for controlling an electrical consumer, the circuit system including an up-down counter, and the circuit system being configured to generate a control signal for controlling the electrical consumer, in particular for shutting off the electrical consumer, as a function of a counter content of the up-down counter. The circuit system includes a controllable clock divider circuit, with the aid of which the circuit system is configured to predefine a counting direction and a counting speed of the up-down counter as a function of at least one variable characterizing an actual current and/or a nominal current of the electrical consumer.

A frequency divider circuit includes: a first latch circuit that including: a pair of input transistors each having a gate thereof configured to connect to a signal line to which a first voltage is supplied; and a pair of output nodes, and configured to receive a single-phase clock signal; and a second latch circuit of SR-type, the second latch circuit having a set input thereof and a reset input thereof configured to connect to the pair of output nodes of the first latch circuit, and configured to output differential clock signals of which frequency is half a frequency of the single-phase clock signal. The first latch circuit is configured to perform amplification and reset operations alternately repeatedly in response to the single-phase clock signal.

Methods and circuits are provided for range extension of a phase-locked loop (PLL). The PLL uses a phase subtractor with a limited unextended range. It also includes first and second registers and combinatorial logic. The phase subtractor calculates the current phase difference. The first register stores the previous phase difference. The combinatorial logic determines, from the current phase difference and the previous phase difference, if a range excursion occurs, and if it is upward or downward. When an upward excursion occurs, the value in the second register is incremented. When a downward excursion occurs, the value of the second register is decremented. The bits in the second register are combined with the bits of the current phase difference to obtain an extended current phase difference.

A signal generation circuit includes a clock divider circuit, an off-pulse generation circuit, and an output signal generation circuit. The on-pulse generation circuit delays an input signal in synchronization with the first and second divided clock signals and generates an even on-pulse signal and an odd on-pulse signal. The off-pulse generation circuit delays the even on-pulse signal and the odd-on pulse signal in synchronization with the first divided clock signal and the second divided clock signal and generates a plurality of delay signals. The output signal generation circuit generates a first pre-output signal based on the delay signals delayed in synchronization with the first divided clock signal, generate a second pre-output signal based on the delay signals delayed in synchronization with the second divided clock signal, and generate an output signal based on the first and second pre-output signals.

Embodiments relates to a layout structure and a method for fabricating the same. A frequency divider pattern layer includes a first frequency divider region, a second frequency divider region, a third frequency divider region and a fourth frequency divider region arranged centrosymmetrically. A conductor pattern layer includes a first sub-conductor pattern layer and a second sub-conductor pattern layer stacked. The first sub-conductor pattern layer is configured to communicate the first frequency divider region with the second frequency divider region, and communicate the third frequency divider region with the fourth frequency divider region. The second sub-conductor pattern layer is configured to communicate the first frequency divider region with the fourth frequency divider region, and communicate the second frequency divider region with the third frequency divider region. The embodiments reduce a channel transmission difference between different frequency dividers in a frequency divider structure.

Embodiments relates to a layout structure and a method for fabricating the same. A frequency divider pattern layer includes a first frequency divider region, a second frequency divider region, a third frequency divider region and a fourth frequency divider region arranged centrosymmetrically. A conductor pattern layer includes a first sub-conductor pattern layer and a second sub-conductor pattern layer stacked. The first sub-conductor pattern layer is configured to communicate the first frequency divider region with the second frequency divider region, and communicate the third frequency divider region with the fourth frequency divider region. The second sub-conductor pattern layer is configured to communicate the first frequency divider region with the fourth frequency divider region, and communicate the second frequency divider region with the third frequency divider region. The embodiments reduce a channel transmission difference between different frequency dividers in a frequency divider structure.

An apparatus of preventing ESD and EMP coupled between a signal input and a signal output is provided with a first diode of forward bias including a positive terminal and a negative terminal connected to the signal input and ground respectively; and a first diode of reverse bias including a negative terminal and a positive terminal connected to the signal input and the ground respectively. The semiconductor is a diode including a p-type semiconductor region made of semiconductor material having a predetermined band gap and an n-type semiconductor region made of semiconductor material having a predetermined band gap. The predetermined band gap is greater than 3 eV. The diode operates in forward bias to discharge current generated by ESD and/or EMP. A method of preventing ESD and EMP is also provided.

An apparatus of preventing ESD and EMP coupled between a signal input and a signal output is provided with a first diode of forward bias including a positive terminal and a negative terminal connected to the signal input and ground respectively; and a first diode of reverse bias including a negative terminal and a positive terminal connected to the signal input and the ground respectively. The semiconductor is a diode including a p-type semiconductor region made of semiconductor material having a predetermined band gap and an n-type semiconductor region made of semiconductor material having a predetermined band gap. The predetermined band gap is greater than 3 eV. The diode operates in forward bias to discharge current generated by ESD and/or EMP. A method of preventing ESD and EMP is also provided.

A spread spectrum clock generating system is provided. The digital frequency detecting unit is configured for receiving a reference signal and a feedback signal and for comparing the reference signal and the feedback signal to generate a frequency difference signal. The digital loop filtering unit is signally connected to the digital frequency detecting unit and outputs a clock controlling signal based on the frequency difference signal. The digital spread spectrum controlling unit is configured for receiving the reference signal to output a spread spectrum signal. The digital-analog converting unit is configured for converting the clock controlling signal to a first controlling signal and for converting the spread spectrum signal to a second controlling signal. The analog controlled oscillating unit is configured for receiving the first controlling signal and the second controlling signal to output a spread spectrum clock signal.

A spread spectrum clock generating system is provided. The digital frequency detecting unit is configured for receiving a reference signal and a feedback signal and for comparing the reference signal and the feedback signal to generate a frequency difference signal. The digital loop filtering unit is signally connected to the digital frequency detecting unit and outputs a clock controlling signal based on the frequency difference signal. The digital spread spectrum controlling unit is configured for receiving the reference signal to output a spread spectrum signal. The digital-analog converting unit is configured for converting the clock controlling signal to a first controlling signal and for converting the spread spectrum signal to a second controlling signal. The analog controlled oscillating unit is configured for receiving the first controlling signal and the second controlling signal to output a spread spectrum clock signal.