A clock generator includes an input coupled to receive an input clock signal from a first clock source, and a noise rejection circuit configured to provide an output clock signal based on the input clock signal. The noise rejection circuit includes an event generator having a digital counter circuit. The event generator is configured to generate a first event signal based on a count value of the digital counter circuit, in which the noise rejection circuit is configured to produce an edge on the output clock signal in response to both the event signal and a state of the input clock signal.

A clock generator includes an input coupled to receive an input clock signal from a first clock source, and a noise rejection circuit configured to provide an output clock signal based on the input clock signal. The noise rejection circuit includes an event generator having a digital counter circuit. The event generator is configured to generate a first event signal based on a count value of the digital counter circuit, in which the noise rejection circuit is configured to produce an edge on the output clock signal in response to both the event signal and a state of the input clock signal.

Provided is a multiplier-accumulator (MAC) system, circuit, and method. The MAC system includes a MAC circuit, including a plurality of resistors, having respective resistances, a capacitor connected to the plurality of resistors to charge, in response to a plurality of input signals, the capacitor with electric charge, and a time-to-digital converter (TDC) configured to convert information of a charge time of the capacitor, due to the electric charge, into a digital value, wherein the digital value is an accumulation result of the MAC circuit.

Provided is a multiplier-accumulator (MAC) system, circuit, and method. The MAC system includes a MAC circuit, including a plurality of resistors, having respective resistances, a capacitor connected to the plurality of resistors to charge, in response to a plurality of input signals, the capacitor with electric charge, and a time-to-digital converter (TDC) configured to convert information of a charge time of the capacitor, due to the electric charge, into a digital value, wherein the digital value is an accumulation result of the MAC circuit.

According to various embodiments, an electronic circuit includes a plurality of clock generators wherein each clock generator is configured to store a counter value, to receive a reference clock, to change the counter value in accordance with the reference clock and to generate at least one clock signal based on the counter value. The circuit also includes a comparator configured to receive, for each of at least two of the plurality of clock generators, the counter value and compare the received counter values and an error handling circuit configured to initiate an error handling based on the result of the comparison.

According to various embodiments, an electronic circuit includes a plurality of clock generators wherein each clock generator is configured to store a counter value, to receive a reference clock, to change the counter value in accordance with the reference clock and to generate at least one clock signal based on the counter value. The circuit also includes a comparator configured to receive, for each of at least two of the plurality of clock generators, the counter value and compare the received counter values and an error handling circuit configured to initiate an error handling based on the result of the comparison.

A “frequency shifter” is a clock synthesis system, that includes either a multiplexer or a multi-modulus divider (MMD), a fractional frequency divider, a tunable delay element, a sawtooth signal generator, in addition to other synchronization and control circuits. The generated sawtooth signal is used to control the delay of the tunable delay element, which in turn is used to adjust the phase of the signal generated by either M-to-1 multiplexer or the MMD, reducing its timing errors, and improving the spectral purity of the generated clock signal.

A “frequency shifter” is a clock synthesis system, that includes either a multiplexer or a multi-modulus divider (MMD), a fractional frequency divider, a tunable delay element, a sawtooth signal generator, in addition to other synchronization and control circuits. The generated sawtooth signal is used to control the delay of the tunable delay element, which in turn is used to adjust the phase of the signal generated by either M-to-1 multiplexer or the MMD, reducing its timing errors, and improving the spectral purity of the generated clock signal.

An analog counter circuit for use with a digital pixel includes an input; an output; a first inverter connected to the input that produces on a first inverter output a time delayed inverted signal (RP*) from an input signal received at the input; a second inverter connected to the first inverter output that produces a time delayed signal (RP) at a second inverter output from the input signal and that is delayed relative to RP* and a control switch connected between a source voltage and a floating node. The control switch is controlled by the signal RP* on the first inverter output. The analog counter also includes a feedback capacitor connected between the second inverter output and the floating node; an accumulating capacitor that accumulates at least some of a charge that passes through the control switch; and an injection switch connected between the control switch and the accumulating capacitor.

An analog counter circuit for use with a digital pixel includes an input; an output; a first inverter connected to the input that produces on a first inverter output a time delayed inverted signal (RP*) from an input signal received at the input; a second inverter connected to the first inverter output that produces a time delayed signal (RP) at a second inverter output from the input signal and that is delayed relative to RP* and a control switch connected between a source voltage and a floating node. The control switch is controlled by the signal RP* on the first inverter output. The analog counter also includes a feedback capacitor connected between the second inverter output and the floating node; an accumulating capacitor that accumulates at least some of a charge that passes through the control switch; and an injection switch connected between the control switch and the accumulating capacitor.