A counter is provided. A charge distributing circuit includes a first switch, a second switch, a third switch, a fourth switch, a third capacitor and a fourth capacitor. A first terminal of the first switch and a first terminal of the third switch are connected to a first input terminal of an operational amplifier. A second terminal of the first switch is connected to a first terminal of the third capacitor and a first terminal of the fourth switch. A second terminal of the third switch is connected to a first terminal of the fourth capacitor and a first terminal of the second switch. A second terminal of the third capacitor and a second terminal of the fourth capacitor are grounded. A second terminal of the second switch and a second terminal of the fourth switch are coupled to a reference voltage.

A counter is provided. A charge distributing circuit includes a first switch, a second switch, a third switch, a fourth switch, a third capacitor and a fourth capacitor. A first terminal of the first switch and a first terminal of the third switch are connected to a first input terminal of an operational amplifier. A second terminal of the first switch is connected to a first terminal of the third capacitor and a first terminal of the fourth switch. A second terminal of the third switch is connected to a first terminal of the fourth capacitor and a first terminal of the second switch. A second terminal of the third capacitor and a second terminal of the fourth capacitor are grounded. A second terminal of the second switch and a second terminal of the fourth switch are coupled to a reference voltage.

A circuit for sensing local operating properties of an integrated circuit is disclosed. The circuit may include one or more sensor circuits configured to sense the local operating properties of the integrated circuit. The sensor circuits may receive a supply voltage with a magnitude in a limited range from a digital power supply that is different from the digital power supply that provides power to functional circuits in the integrated circuit. Level shifters may be coupled to the sensor circuits to shift output signals from the sensor circuits to levels that correspond to the digital power supply that provides power to functional circuits in the integrated circuit. Counters and a shift register may be coupled to the level shifters to receive the shifted output signals, the values of which may be used to determine the local operating properties of the integrated circuit as sensed by the sensor circuits.

A circuit for sensing local operating properties of an integrated circuit is disclosed. The circuit may include one or more sensor circuits configured to sense the local operating properties of the integrated circuit. The sensor circuits may receive a supply voltage with a magnitude in a limited range from a digital power supply that is different from the digital power supply that provides power to functional circuits in the integrated circuit. Level shifters may be coupled to the sensor circuits to shift output signals from the sensor circuits to levels that correspond to the digital power supply that provides power to functional circuits in the integrated circuit. Counters and a shift register may be coupled to the level shifters to receive the shifted output signals, the values of which may be used to determine the local operating properties of the integrated circuit as sensed by the sensor circuits.

An offset detector circuit includes a digital signal register storing M unit digital signals received in latest M signal periods, M being a natural number, among digital signals generated based on a single-ended PAM-N signal, N being an odd number, a comparator outputting a comparison signal of a pair of signals included in differential signals generated from a differential signal generator based on the single-ended PAM-N signal, a comparison result register storing M unit comparison signals corresponding to the latest M signal periods among the comparison signals, a pattern detector outputting a detection signal when the M unit digital signals match a predetermined signal pattern, and an offset checker checking patterns of the M unit comparison signals in response to the detection signal, and outputting an offset detection signal when the patterns of the M unit comparison signals match a predetermined offset pattern.

An offset detector circuit includes a digital signal register storing M unit digital signals received in latest M signal periods, M being a natural number, among digital signals generated based on a single-ended PAM-N signal, N being an odd number, a comparator outputting a comparison signal of a pair of signals included in differential signals generated from a differential signal generator based on the single-ended PAM-N signal, a comparison result register storing M unit comparison signals corresponding to the latest M signal periods among the comparison signals, a pattern detector outputting a detection signal when the M unit digital signals match a predetermined signal pattern, and an offset checker checking patterns of the M unit comparison signals in response to the detection signal, and outputting an offset detection signal when the patterns of the M unit comparison signals match a predetermined offset pattern.

An electronic device comprising one or more subcircuits configured to receive a clock signal, the clock signal configured to switch from a reference clock signal to a second clock signal based on a clock bypass signal, a timer configured to receive the reference clock signal and output an alignment signal based on the reference clock signal, wherein a frequency of the alignment signal is determined based on clock frequencies of the one or more subcircuits; a clock alignment module coupled to the timer and the one or more subcircuits and configured to receive the clock bypass signal, determine that the clock bypass signal has changed to switch the one or more subcircuits to the reference clock signal from the second clock signal, block the clock signal from being received by the one or more subcircuits, receive the alignment signal, and unblock the clock signal based on the alignment signal.

An electronic device comprising one or more subcircuits configured to receive a clock signal, the clock signal configured to switch from a reference clock signal to a second clock signal based on a clock bypass signal, a timer configured to receive the reference clock signal and output an alignment signal based on the reference clock signal, wherein a frequency of the alignment signal is determined based on clock frequencies of the one or more subcircuits; a clock alignment module coupled to the timer and the one or more subcircuits and configured to receive the clock bypass signal, determine that the clock bypass signal has changed to switch the one or more subcircuits to the reference clock signal from the second clock signal, block the clock signal from being received by the one or more subcircuits, receive the alignment signal, and unblock the clock signal based on the alignment signal.

A lightning strike counter and a lightning strike counting method are disclosed. The lightning strike counter includes a lightning strike input circuit, a bipolar waveform generating circuit, and a counting circuit. The lightning strike input circuit receives a lightning strike signal from a first lightning strike input end and a second lightning strike input end. The bipolar waveform generating circuit outputs a bipolar waveform signal from a bipolar waveform output end to the counting circuit in response to the lightning strike input circuit receiving the lightning strike signal. The counting circuit outputs a counting output signal from a counting output end in response to receiving the bipolar waveform signal from a counting input end.

A lightning strike counter and a lightning strike counting method are disclosed. The lightning strike counter includes a lightning strike input circuit, a bipolar waveform generating circuit, and a counting circuit. The lightning strike input circuit receives a lightning strike signal from a first lightning strike input end and a second lightning strike input end. The bipolar waveform generating circuit outputs a bipolar waveform signal from a bipolar waveform output end to the counting circuit in response to the lightning strike input circuit receiving the lightning strike signal. The counting circuit outputs a counting output signal from a counting output end in response to receiving the bipolar waveform signal from a counting input end.