Aspects of the disclosure include an integrated circuit that includes a first circuit, a first performance detector, and a first regulator. The first circuit is configured to receive a first regulated voltage from a first voltage supply line disposed on the integrated circuit. The first performance detector includes a first speed monitor disposed adjacent to the first circuit, and the first performance detector is configured to generate a first control signal based on a first speed detection result from the first speed monitor. The first speed detection result corresponds to measuring an operational speed of the first circuit. The first regulator is configured to receive a global supply voltage from a power rail and output the first regulated voltage based on the global supply voltage and the first control signal.

Aspects of the disclosure include an integrated circuit that includes a first circuit, a first performance detector, and a first regulator. The first circuit is configured to receive a first regulated voltage from a first voltage supply line disposed on the integrated circuit. The first performance detector includes a first speed monitor disposed adjacent to the first circuit, and the first performance detector is configured to generate a first control signal based on a first speed detection result from the first speed monitor. The first speed detection result corresponds to measuring an operational speed of the first circuit. The first regulator is configured to receive a global supply voltage from a power rail and output the first regulated voltage based on the global supply voltage and the first control signal.

The invention relates to a device and to a method for producing a signal having an adjustable pulse duty factor, in particular a pulse-width-modulated signal. For this purpose, the period duration of the pulse-width-modulated signal can be varied. Thus, the pulse duty factor of the pulse-width-modulated signal can be adapted very accurately to the desired pulse duty factor without great switching complexity by using a simple counter with a fixed clock frequency.

The invention relates to a device and to a method for producing a signal having an adjustable pulse duty factor, in particular a pulse-width-modulated signal. For this purpose, the period duration of the pulse-width-modulated signal can be varied. Thus, the pulse duty factor of the pulse-width-modulated signal can be adapted very accurately to the desired pulse duty factor without great switching complexity by using a simple counter with a fixed clock frequency.

An embodiment method for modifying the frequency of a clock signal clocking an integrated circuit supplied by a voltage controller comprises, in response to a command for the modification, varying the frequency of the clock signal at a rate allowing a supply voltage to be controlled by the controller. The variation comprises at least one series of successive divisions of the frequency of the clock signal into successive intermediate signals of respective intermediate frequencies.

In described examples, a counter system includes a counter, a parity detector, a toggle flop, and a comparator. The counter iterates a count through a set of binary states in response to a clock signal, so that a binary value of a single bit of the count changes at each iteration. The parity detector detects the parity of the count. The toggle flop output is coupled to the toggle flop input. The toggle flop outputs a binary flop value. The binary flop value toggles between zero and one in response to the toggle flop input and the clock signal. The comparator compares the parity of the count and the toggle flop output, and outputs a first comparator value if the parity of the count and the toggle flop output are the same, and a second comparator value if the parity of the count and the toggle flop output are different.

In described examples, a counter system includes a counter, a parity detector, a toggle flop, and a comparator. The counter iterates a count through a set of binary states in response to a clock signal, so that a binary value of a single bit of the count changes at each iteration. The parity detector detects the parity of the count. The toggle flop output is coupled to the toggle flop input. The toggle flop outputs a binary flop value. The binary flop value toggles between zero and one in response to the toggle flop input and the clock signal. The comparator compares the parity of the count and the toggle flop output, and outputs a first comparator value if the parity of the count and the toggle flop output are the same, and a second comparator value if the parity of the count and the toggle flop output are different.

A divider and buffer circuit uses a receive command to initiate a reset of buffer circuitry prior to restarting to avoid a metastable state. For example, the divider and buffer circuit includes a first buffer circuit, a second buffer circuit, and a reset circuit. The reset circuit receives a command and provide a pulse on a reset signal in response to the command. In response to the reset pulse, the first buffer circuit provides a first divided clock signal having a first logical value based on respective logical values of received complementary clock signals and the second buffer circuit provides a second divided clock signal having a second logical value based on the respective logical values of the complementary clock signals. The command is a CAS SYNC command, in some examples.

A divider and buffer circuit uses a receive command to initiate a reset of buffer circuitry prior to restarting to avoid a metastable state. For example, the divider and buffer circuit includes a first buffer circuit, a second buffer circuit, and a reset circuit. The reset circuit receives a command and provide a pulse on a reset signal in response to the command. In response to the reset pulse, the first buffer circuit provides a first divided clock signal having a first logical value based on respective logical values of received complementary clock signals and the second buffer circuit provides a second divided clock signal having a second logical value based on the respective logical values of the complementary clock signals. The command is a CAS SYNC command, in some examples.

Disclosed herein is an apparatus that includes a first circuit configured to generate a first signal a first number of times in response to an input signal, a second circuit configured to generate a second signal having a second numerical value each time the first signal is activated, and a third circuit configured to receive the second signal to update a count value obtained by accumulating the second numerical value, configured to generate a third signal each time the count value reaches a third numerical value, and configured to update the count value obtained by accumulating the second numerical value and subtracting the third numerical value when the count value reached the third numerical value.