The invention relates to a frequency multiplying device for determination of a fundamental frequency f of an analogue target signal. The device comprises a generating device for generating a reference signal having a frequency f.sub.osc, wherein f.sub.osc is greater than f, and a first counter being coupled to a terminal, the terminal to be fed with the analogue target signal, and being coupled to the generating device such that the first counter counts a number of signal edges generated from the reference signal in a time interval corresponding substantially to 1/f and outputs a first counter signal, wherein a frequency divider is coupled between the generating device and the first counter and a second counter is coupled to the generating device for counting signal edges of a signal generated from the reference signal the second counter outputting a second counter signal and a comparator is coupled to the first counter to receive the first counter signal and coupled to the second counter to receive the second counter signal, wherein the comparator generates a signal in the event the first counter signal is equal to the second counter signal, and the output of the comparator is coupled to reset the second counter.

The invention relates to a frequency multiplying device for determination of a fundamental frequency f of an analogue target signal. The device comprises a generating device for generating a reference signal having a frequency f.sub.osc, wherein f.sub.osc is greater than f, and a first counter being coupled to a terminal, the terminal to be fed with the analogue target signal, and being coupled to the generating device such that the first counter counts a number of signal edges generated from the reference signal in a time interval corresponding substantially to 1/f and outputs a first counter signal, wherein a frequency divider is coupled between the generating device and the first counter and a second counter is coupled to the generating device for counting signal edges of a signal generated from the reference signal the second counter outputting a second counter signal and a comparator is coupled to the first counter to receive the first counter signal and coupled to the second counter to receive the second counter signal, wherein the comparator generates a signal in the event the first counter signal is equal to the second counter signal, and the output of the comparator is coupled to reset the second counter.

A method for modifying the frequency of a clock signal clocking an integrated circuit supplied by a voltage controller, comprises, in response to a command for the modification, varying the frequency of the clock signal at a rate allowing a supply voltage to be controlled by the controller. The variation comprises at least one series of successive divisions of the frequency of the clock signal into successive intermediate signals of respective intermediate frequencies.

To improve a timing error detection accuracy in a semiconductor integrated circuit provided with storage devices operating in synchronization with a clock signal. A delay part delays a data signal by two mutually-different delay times and outputs it as first and second delay signals. A holding part holds the first and second delay signals in synchronization with a timing signal for giving an instruction on a predetermined capture timing. A setup time detection part detects whether or not one of the first and second delay signals held within a setup-time detection period from a predetermined start timing to the predetermined capture timing has changed. A hold time detection part detects whether or not the other of the first and second delay signals held within a hold-time detection period from the predetermined capture timing to a predetermined end timing has changed.

A time-to-digital converter obtains a Start signal to indicate the start of an event, and a Stop signal whose assertion indicates the stop of the event. The Stop signal can be asserted multiple times due to false indications of the event stop. The TDC continuously monitors the Stop signal to generate a separate digital value for the duration from the event's starting time to each assertion of the Stop signal. The digital values can be analyzed to select the true duration of the event. Other features and embodiments are also provided.

A time-to-digital converter obtains a Start signal to indicate the start of an event, and a Stop signal whose assertion indicates the stop of the event. The Stop signal can be asserted multiple times due to false indications of the event stop. The TDC continuously monitors the Stop signal to generate a separate digital value for the duration from the event's starting time to each assertion of the Stop signal. The digital values can be analyzed to select the true duration of the event. Other features and embodiments are also provided.

An analog counter circuit for use with a digital pixel includes an input; an output; a first inverter connected to the input that produces on a first inverter output a time delayed inverted signal (RP*) from an input signal received at the input; a second inverter connected to the first inverter output that produces a time delayed signal (RP) at a second inverter output from the input signal and that is delayed relative to RP* and a control switch connected between a source voltage and a floating node. The control switch is controlled by the signal RP* on the first inverter output. The analog counter also includes a feedback capacitor connected between the second inverter output and the floating node; an accumulating capacitor that accumulates at least some of a charge that passes through the control switch; and an injection switch connected between the control switch and the accumulating capacitor.

An analog counter circuit for use with a digital pixel includes an input; an output; a first inverter connected to the input that produces on a first inverter output a time delayed inverted signal (RP*) from an input signal received at the input; a second inverter connected to the first inverter output that produces a time delayed signal (RP) at a second inverter output from the input signal and that is delayed relative to RP* and a control switch connected between a source voltage and a floating node. The control switch is controlled by the signal RP* on the first inverter output. The analog counter also includes a feedback capacitor connected between the second inverter output and the floating node; an accumulating capacitor that accumulates at least some of a charge that passes through the control switch; and an injection switch connected between the control switch and the accumulating capacitor.

An analog counter circuit for use with a digital pixel includes: an input; an output; a first stage electrically coupled to the input that is charged to an initial charge voltage; a second stage that includes an accumulating charge storage device; and a charge transfer device between the first and second stages that includes a transfer voltage. The charge transfer device allows charge from the first stage to pass to the second stage and be accumulated on the accumulating charge storage device as long as a voltage at a node in the first stage is greater than the transfer voltage.

An analog counter circuit for use with a digital pixel includes: an input; an output; a first stage electrically coupled to the input that is charged to an initial charge voltage; a second stage that includes an accumulating charge storage device; and a charge transfer device between the first and second stages that includes a transfer voltage. The charge transfer device allows charge from the first stage to pass to the second stage and be accumulated on the accumulating charge storage device as long as a voltage at a node in the first stage is greater than the transfer voltage.