A digital frequency measuring apparatus includes a frequency divider dividing an input frequency signal and providing a divided frequency signal; a period counter counting clock cycles in a period of the divided frequency signal using a clock signal and providing a period count value for each period; and a digital filter amplifying the period count value using an accumulated gain, converting an amplified period count value into a frequency, and providing a first digital output value. The digital filter determines the accumulated gain using a predetermined stage number and a predetermined decimator factor.

The present application relates to a circuit of a frequency divider arranged to divide a frequency of an input clock signal by odd integer N and a method of operating the circuit. A shift register comprises a number of N+1 clock gating cells, which are connected in series to each other, and a shift logic. An input clock signal is fed into clock signal inputs of each one of the number of N+1 clock gating cells. The shift logic is configured to receive enable signals from a set of the number of N+1 clock gating cells and to generate a feedback signal, which is supplied to a gate enable input of the first one of the number of N+1 clock gating cells. A multiplexer is configured to receive at input ports N+1 gated clock signals and to output a rotation clock signal, which has a frequency of 2/N of the frequency of the input clock signal. A frequency generator is configured to receive the rotation clock signal and to generate an output clock signal having a frequency of 1/N.

Apparatuses for performing combination logic operations with a combination logic circuit are disclosed. According to one embodiment, the apparatus comprises a first-in-first-out stage comprising an combination logic circuit, a input ring counter circuit coupled to the first-in-first-out stage and configured to selectively provide a push signal to the first-in-first-out stage, and a output ring counter circuit coupled to the first-in-first-out stage and configured to selectively provide a pop signal to the first-in-first-out stage, wherein the first-in-first-out stage is configured to perform calculations on input data with the combination logic circuit to generate output data responsive to receiving the push signal and to provide the output data based on the calculations responsive to receiving the pop signal.

Apparatuses for performing combination logic operations with a combination logic circuit are disclosed. According to one embodiment, the apparatus comprises a first-in-first-out stage comprising an combination logic circuit, a input ring counter circuit coupled to the first-in-first-out stage and configured to selectively provide a push signal to the first-in-first-out stage, and a output ring counter circuit coupled to the first-in-first-out stage and configured to selectively provide a pop signal to the first-in-first-out stage, wherein the first-in-first-out stage is configured to perform calculations on input data with the combination logic circuit to generate output data responsive to receiving the push signal and to provide the output data based on the calculations responsive to receiving the pop signal.

Aspects of the disclosure are directed to reducing clock-ungating induced voltage droop by determining a maximum frequency value associated with an output clock waveform; modulating a clock frequency of the output clock waveform for a first time duration based on a first programmable mask pattern or a first Boolean function; and determining if either the first programmable mask pattern or the first Boolean function should be changed. In accordance with one aspect, a voltage droop mitigation circuit includes a control logic for receiving an input clock waveform and a clock enable signal waveform and for outputting a gated clock enable signal waveform; a latch coupled to the control logic, the latch for holding a state of the gated clock enable signal waveform and a AND gate coupled to the latch, the AND gate for outputting an output clock waveform.

A buffer system may have an output for driving a switched load that changes during periods indicated by a switching signal. The buffer system may operate in a closed loop when the switching signal indicates that a load change is not taking place by comparing a signal indicative of the output of the buffer system with a reference voltage. The buffer system may operate in an open loop when the switching signal indicates that a load change is taking place by not comparing signal indicative of the output of the buffer system with the reference voltage. Both the buffer system and the switched load may be on the same chip.

A buffer system may have an output for driving a switched load that changes during periods indicated by a switching signal. The buffer system may operate in a closed loop when the switching signal indicates that a load change is not taking place by comparing a signal indicative of the output of the buffer system with a reference voltage. The buffer system may operate in an open loop when the switching signal indicates that a load change is taking place by not comparing signal indicative of the output of the buffer system with the reference voltage. Both the buffer system and the switched load may be on the same chip.

The present application relates to a circuit of a frequency divider arranged to divide a frequency of an input clock signal by odd integer N and a method of operating the circuit. A shift register comprises a number of N+1 clock gating cells, which are connected in series to each other, and a shift logic. An input clock signal is fed into clock signal inputs of each one of the number of N+1 clock gating cells. The shift logic is configured to receive enable signals from a set of the number of N+1 clock gating cells and to generate a feedback signal, which is supplied to a gate enable input of the first one of the number of N+1 clock gating cells. A multiplexer is configured to receive at input ports N+1 gated clock signals and to output a rotation clock signal, which has a frequency of 2/N of the frequency of the input clock signal. A frequency generator is configured to receive the rotation clock signal and to generate an output clock signal having a frequency of 1/N.

The present application relates to a system hosting a monotonic counter and a method of operating the system. The system comprises a non-volatile memory (110) for holding a save counter value and a volatile memory (120) for maintaining a current counter value. The system (100) is configured during a startup phase to retrieve the saved counter value of the monotonic counter from the non-volatile memory (110); to detect whether a previous shutdown of the system (100) was an uncontrolled shutdown; and to adjust the retrieved counter value in accordance with a step size (130) provided at the system (100) in case an previous uncontrolled shutdown is detected.

A method for implementing a non-volatile counter using non-volatile memory is disclosed. In an embodiment, the method involves distributing operations for storing a low word of a counter in non-volatile memory across memory cells in a memory array in the non-volatile memory, and storing additional bits of the counter in the non-volatile memory in memory cells outside of the memory array, wherein the location in the memory array at which the low word is stored is determined for each count based on the upper bits of the counter.