Programmable timer circuits are disclosed. One timer circuit may include a reference circuit configured to generate a bias current, a current controlled oscillator configured to receive the bias current c, and a frequency divider network configured to divide an output of the oscillator. The timer circuit may be capable of timing for 24 hour period, while using less than 5nA of quiescent current.

Programmable timer circuits are disclosed. One timer circuit may include a reference circuit configured to generate a bias current, a current controlled oscillator configured to receive the bias current c, and a frequency divider network configured to divide an output of the oscillator. The timer circuit may be capable of timing for 24 hour period, while using less than 5nA of quiescent current.

A programmable divider is provided. The programmable divider includes a clock input coupled to receive a clock signal, a control input coupled to receive a first control signal, a counter compare block, and a load block. The counter compare block is configured to receive a first load value, update a counter with the first load value, provide a first output signal, and when the first control signal is at a first value, generate a first pulse in the first output signal when the counter reaches an end value. The load block is configured to receive a first divider value and provide the first load value based on a current counter value of the counter.

A programmable divider is provided. The programmable divider includes a clock input coupled to receive a clock signal, a control input coupled to receive a first control signal, a counter compare block, and a load block. The counter compare block is configured to receive a first load value, update a counter with the first load value, provide a first output signal, and when the first control signal is at a first value, generate a first pulse in the first output signal when the counter reaches an end value. The load block is configured to receive a first divider value and provide the first load value based on a current counter value of the counter.

Memory devices and methods utilize pipelines to process or control timing of commands received by the memory device. They may also use tracking circuitry configured to determine whether one or more of the commands are in the pipeline. The tracking circuitry includes an input counter configured to count commands entering into the pipeline and an output counter configured to count commands exiting the pipeline. Furthermore, the tracking circuitry includes comparison circuitry configured to compare values in the input counter and the output counter and to output a command-in-pipeline signal indicative of the one or more commands being in the pipeline when the values in the input counter and the output counter differ.

Memory devices and methods utilize pipelines to process or control timing of commands received by the memory device. They may also use tracking circuitry configured to determine whether one or more of the commands are in the pipeline. The tracking circuitry includes an input counter configured to count commands entering into the pipeline and an output counter configured to count commands exiting the pipeline. Furthermore, the tracking circuitry includes comparison circuitry configured to compare values in the input counter and the output counter and to output a command-in-pipeline signal indicative of the one or more commands being in the pipeline when the values in the input counter and the output counter differ.

Memory devices and methods utilize pipelines to process or control timing of commands received by the memory device. They may also use tracking circuitry configured to determine whether one or more of the commands are in the pipeline. The tracking circuitry includes an input counter configured to count commands entering into the pipeline and an output counter configured to count commands exiting the pipeline. Furthermore, the tracking circuitry includes comparison circuitry configured to compare values in the input counter and the output counter and to output a command-in-pipeline signal indicative of the one or more commands being in the pipeline when the values in the input counter and the output counter differ.

Memory devices and methods utilize pipelines to process or control timing of commands received by the memory device. They may also use tracking circuitry configured to determine whether one or more of the commands are in the pipeline. The tracking circuitry includes an input counter configured to count commands entering into the pipeline and an output counter configured to count commands exiting the pipeline. Furthermore, the tracking circuitry includes comparison circuitry configured to compare values in the input counter and the output counter and to output a command-in-pipeline signal indicative of the one or more commands being in the pipeline when the values in the input counter and the output counter differ.

In a phase locked loop composed of digital circuits, the circuit scale of a circuit that generates phase difference information is reduced. A multi-phase clock generation circuit generates a plurality of feedback clock signals having different phases. A feedback side frequency divider divides frequencies of the plurality of feedback clock signals and outputs the feedback clock signals as frequency-divided clock signals. A reference clock latch circuit holds the frequency-divided clock signals in synchronization with a reference clock signal and outputs a held value. A control circuit controls the frequencies of the plurality of feedback clock signals on the basis of the held value.

The power of a semiconductor device is reduced. The semiconductor device includes a latch circuit composed of a dynamic circuit. The latch circuit includes a first circuit having a decoding function, a plurality of capacitors, a plurality of clock input terminals, a signal input terminal, a first output terminal, and a second output terminal. In a period during which H is supplied to a first clock signal, the potential of the first capacitor is updated on the basis of the results of decoding performed by the first circuit. In a period during which H is supplied to a second clock signal, the potential of the second capacitor is updated on the basis of the potential of the first capacitor, and the potential of the second capacitor is supplied as a first output signal to the first output terminal. In a period during which H is supplied to a third clock signal, the potential of the third capacitor is updated on the basis of the potential of the second capacitor, and the potential of the third capacitor is supplied as a second output signal to the second output terminal.