A clock filter filtering a glitch of an input clock to generate an output clock is provided. A first delay circuit inverts the input clock to generate an inverted clock and delays the inverted clock to generate a first processing clock. A second delay circuit delays the input clock to generate a second processing clock. A first setting circuit generates a reset clock according to the inverted clock and the first processing clock. A second setting circuit generates a set clock according to the input clock and the second processing clock. When the set clock changes from a first level to a second level, a third setting circuit sets the output clock at the second level. When the reset clock changes from the first level to the second level, the third setting circuit sets the output clock to the first level.

A clock filter filtering a glitch of an input clock to generate an output clock is provided. A first delay circuit inverts the input clock to generate an inverted clock and delays the inverted clock to generate a first processing clock. A second delay circuit delays the input clock to generate a second processing clock. A first setting circuit generates a reset clock according to the inverted clock and the first processing clock. A second setting circuit generates a set clock according to the input clock and the second processing clock. When the set clock changes from a first level to a second level, a third setting circuit sets the output clock at the second level. When the reset clock changes from the first level to the second level, the third setting circuit sets the output clock to the first level.

A counter circuit includes multiple stages of counting circuits corresponding to binary bits, each stage being configured to: obtain a carry signal and a this-time bit value according to an addend signal and a bit value currently output by the stage, output the carry signal to a next-stage counting circuit, latch the this-time bit value in response to a first clock and output same to an output terminal of the stage of counting circuit in response to a second clock. An output of the counter circuit is composed of bit values output by the multiple stages and is a binary representation of a counting result. An addend signal of a start-stage counting circuit is a high-level signal and an addend signal of a non-start-stage counting circuit is a carry signal output by an immediately previous stage. The first and second clocks are obtained based on division of a system clock.

A counter circuit includes multiple stages of counting circuits corresponding to binary bits, each stage being configured to: obtain a carry signal and a this-time bit value according to an addend signal and a bit value currently output by the stage, output the carry signal to a next-stage counting circuit, latch the this-time bit value in response to a first clock and output same to an output terminal of the stage of counting circuit in response to a second clock. An output of the counter circuit is composed of bit values output by the multiple stages and is a binary representation of a counting result. An addend signal of a start-stage counting circuit is a high-level signal and an addend signal of a non-start-stage counting circuit is a carry signal output by an immediately previous stage. The first and second clocks are obtained based on division of a system clock.

Apparatuses and techniques for counting 0 or 1 bits in a set of bits using both serial and parallel processes. The counting process includes a hierarchy in which the count from different parallel processes at one level in the hierarchy are passed to a smaller number of different parallel processes at a lower level in the hierarchy. A final count is obtained by an accumulator below the lowest level of the hierarchy. The position and configuration of the circuits can be set to equalize a number of circuits which process the different bits, so that a maximum delay relative to the accumulator is equalized.

Apparatuses and techniques for counting 0 or 1 bits in a set of bits using both serial and parallel processes. The counting process includes a hierarchy in which the count from different parallel processes at one level in the hierarchy are passed to a smaller number of different parallel processes at a lower level in the hierarchy. A final count is obtained by an accumulator below the lowest level of the hierarchy. The position and configuration of the circuits can be set to equalize a number of circuits which process the different bits, so that a maximum delay relative to the accumulator is equalized.

Novel unipolar circuits and vertical structures are described which exhibit low stand-by power, low dynamic power, high speed performance, and have higher density compared to conventional silicon CMOS circuitry. In one embodiment, a design methodology utilizing either a p-channel or n-channel transistor type such that each logic gate is clocked and the clocking mechanism provides the pull up or pull down. Further embodiments include novel designs of vertical unipolar logic gates which provides for high density. Ultra-short transistor channel lengths in vertical unipolar logic gates are fabricated with a deposition processin lieu of a lithography processthereby providing for high speed operation and low cost manufacturing.

The present invention provides a frequency-halving latch circuit for deterministic field bus network data forwarding and application thereof. The frequency-halving latch circuit includes a data buffer equipped with two buffer units; a frequency-halving enable latch signal generation module for generating a first frequency-halving latch signal and a second frequency-halving latch signal with opposite levels, and selecting data buffer units of the data buffer based on the first frequency-halving latch signal, the second frequency-halving latch signal and a receiving enable signal; and a shift register including a first trigger and a second trigger which are initialized to opposite output states, the first trigger and the second trigger is connected to realize a shift operation, and data stored in the data buffer units is finally selected and read based on a low order in the shift register composed of the two triggers and a read enable signal. The frequency-halving latch circuit can be applied to a scenario of deterministic field bus network data forwarding as a same-frequency out-of-phase data cross-clock domain circuit, with high resource utilization rate and stability.

The present invention provides a frequency-halving latch circuit for deterministic field bus network data forwarding and application thereof. The frequency-halving latch circuit includes a data buffer equipped with two buffer units; a frequency-halving enable latch signal generation module for generating a first frequency-halving latch signal and a second frequency-halving latch signal with opposite levels, and selecting data buffer units of the data buffer based on the first frequency-halving latch signal, the second frequency-halving latch signal and a receiving enable signal; and a shift register including a first trigger and a second trigger which are initialized to opposite output states, the first trigger and the second trigger is connected to realize a shift operation, and data stored in the data buffer units is finally selected and read based on a low order in the shift register composed of the two triggers and a read enable signal. The frequency-halving latch circuit can be applied to a scenario of deterministic field bus network data forwarding as a same-frequency out-of-phase data cross-clock domain circuit, with high resource utilization rate and stability.

Temporal history of voltage supply level enveloping high-speed transient events is provided by circuitry on the same chip or in the same multi-chip module as the processor cores. In some embodiments supply voltage to the processor cores is compared to predetermined or programmable thresholds, and the result of the comparisons are stored for use by a host processor.