An inductor-less local oscillator (LO) signal generation apparatus configured to generate one or more output signals which reduce a frequency pulling effect. The LO signal generation apparatus includes a multi-phase signal generation circuit, a phase signal generation circuit and one or more output circuits. The multi-phase signal generation circuit receives an input clock signal having a first frequency to generate a multi-phase clock signal. The multi-phase clock signal includes a plurality of clock signals each having the first frequency and different phases. The phase signal generation circuit is coupled to the multi-phase signal generation circuit to receive the multi-phase clock signal and output a plurality of phase signals indicating the phases of the clock signals. The one or more output circuits output the one or more output signals according to the clock signals and the phase signals without receiving feedback of any of the one or more output signals.

An inductor-less local oscillator (LO) signal generation apparatus configured to generate one or more output signals which reduce a frequency pulling effect. The LO signal generation apparatus includes a multi-phase signal generation circuit, a phase signal generation circuit and one or more output circuits. The multi-phase signal generation circuit receives an input clock signal having a first frequency to generate a multi-phase clock signal. The multi-phase clock signal includes a plurality of clock signals each having the first frequency and different phases. The phase signal generation circuit is coupled to the multi-phase signal generation circuit to receive the multi-phase clock signal and output a plurality of phase signals indicating the phases of the clock signals. The one or more output circuits output the one or more output signals according to the clock signals and the phase signals without receiving feedback of any of the one or more output signals.

Programmable timer circuits are disclosed. One timer circuit may include a reference circuit configured to generate a bias current, a current controlled oscillator configured to receive the bias current c, and a frequency divider network configured to divide an output of the oscillator. The timer circuit may be capable of timing for 24 hour period, while using less than 5nA of quiescent current.

Disclosed is a frequency divider which includes a frequency dividing core circuit that includes a plurality of transistors and is configured to generate at least one division clock signal based on a clock signal and an inverted clock signal, a controller that is configured to generate a body bias control signal based on clock frequency information, and an adaptive body bias (ABB) generator that is configured to generate at least one body bias based on the body bias control signal and configured to apply the at least one body bias to a body of one or more of the plurality of transistors.

Disclosed is a frequency divider which includes a frequency dividing core circuit that includes a plurality of transistors and is configured to generate at least one division clock signal based on a clock signal and an inverted clock signal, a controller that is configured to generate a body bias control signal based on clock frequency information, and an adaptive body bias (ABB) generator that is configured to generate at least one body bias based on the body bias control signal and configured to apply the at least one body bias to a body of one or more of the plurality of transistors.

A frequency divider includes a first shifter and a second shifter. The first shifter includes first to M-th clock control components connected together to form a first ring. The control components in the first shifter are controlled by an input clock signal such that signals are shifted along the first ring. An output of selected clock control components in the first shifter is provided as a carry signal of the first shifter. The second shifter includes first to N-th clock control components connected together to form a second ring. The control components in the second shifter are controlled by the carry signal of the first shifter such that the signals are shifted along the second ring. An output of selected clock control components in the second shifter is provided as a carry signal of the second shifter. M and N are integers greater than one.

Frequency divider techniques are disclosed which can be used to address two problems: when an incorrect division occurs if the modulus control changes before the divide cycle is complete, and when an incorrect division occurs due to a boundary crossing (e.g., power-of-2 boundary crossing in a fractional-N PLL application). In one embodiment, a frequency divider is provided comprising a plurality of flip-flops operatively coupled to carry out division of an input frequency, and configured to generate a modulus output and receive a divided clock signal of a previous cell. An additional flip-flop is selectively clocked off one of the modulus output or the divided clock of the previous stage, depending at least in part on a Skip control signal applied to a data input of the additional flip-flop, and is further configured to selectively reset the plurality of flip-flops to a state that will result in a correct divide ratio.

In described examples, an apparatus includes: a counter configured to receive a reference clock signal and having a next state input and a current state output; a multiplexer coupled to the next state input of the counter, configured to output one of an incremented next state value and a corrected next state count value responsive to a count correction select control signal; a seconds reference circuit coupled to the current state output of the counter, configured to output a seconds reference signal; an incrementer coupled to the current state output of the counter, configured to output the incremented next state value; and a calibration compensation circuit coupled to a compensate up down input signal and to the current state output of the counter, configured to output the corrected next state count value and the count correction select control signal.

In described examples, an apparatus includes: a counter configured to receive a reference clock signal and having a next state input and a current state output; a multiplexer coupled to the next state input of the counter, configured to output one of an incremented next state value and a corrected next state count value responsive to a count correction select control signal; a seconds reference circuit coupled to the current state output of the counter, configured to output a seconds reference signal; an incrementer coupled to the current state output of the counter, configured to output the incremented next state value; and a calibration compensation circuit coupled to a compensate up down input signal and to the current state output of the counter, configured to output the corrected next state count value and the count correction select control signal.

A driving signal control circuit includes a discharge circuit, a counter circuit, and a control circuit. The discharge circuit is configured to compare a monitored voltage and a reference voltage, and generate a discharge signal. The monitored voltage is proportional to a core voltage. The counter circuit is configured to perform an up/down count operation according to the discharge signal, and generate a count signal. The control circuit is configured to generate a driving signal which has an enable period proportional to the count signal.