A fractional frequency divider comprises: a fractional frequency divider circuit configured to, by using an integer frequency division signal obtained by dividing an input signal by an integer frequency division ratio, generate a fractional frequency division signal into which the input signal is divided by a fraction frequency division ratio; a latch circuit configured to capture a frequency control signal representing a specified fraction frequency division ratio in synchronization with the fractional frequency division signal; and a control circuit configured to generate an integer control signal for setting an integer frequency division ratio corresponding to a specified fraction frequency division ratio in synchronization with an integer frequency division signal, based on a captured frequency control signal. The fractional frequency divider circuit updates the integer frequency division ratio by referring to the integer control signal in synchronization with the input signal.

A fractional frequency divider comprises: a fractional frequency divider circuit configured to, by using an integer frequency division signal obtained by dividing an input signal by an integer frequency division ratio, generate a fractional frequency division signal into which the input signal is divided by a fraction frequency division ratio; a latch circuit configured to capture a frequency control signal representing a specified fraction frequency division ratio in synchronization with the fractional frequency division signal; and a control circuit configured to generate an integer control signal for setting an integer frequency division ratio corresponding to a specified fraction frequency division ratio in synchronization with an integer frequency division signal, based on a captured frequency control signal. The fractional frequency divider circuit updates the integer frequency division ratio by referring to the integer control signal in synchronization with the input signal.

Various embodiments relate to multi-modulus frequency dividers, devices including the same, and associated methods of operation. A method of operating a multi-modulus divider (MMD) may include receiving, at the MMD, an input signal at a first frequency. The method may also include generating, via the MMD, an output signal at a second, lower frequency based on a divisor value. Further, the method may include receiving, at the MMD, an integer value. Moreover, the method may include setting the divisor value equal to the integer value in response to a current state of the MMD matching a common state for the MMD, wherein the MMD is configured to enter the common state regardless of the divisor value.

Various embodiments relate to multi-modulus frequency dividers, devices including the same, and associated methods of operation. A method of operating a multi-modulus divider (MMD) may include determining a common state for the MMD, wherein the MMD is configured to enter the common state regardless of a divisor value applied to the MMD. The method may further include receiving an integer value at the MMD. Further, the method may include setting the divisor value equal to the integer value. The method may also include receiving an input signal at a first frequency and generating an output signal at a second, lower frequency based on the divisor value. The method may also include receiving a second integer value at the MMD. The method may further include setting the divisor value equal to the second integer value in response to a detected current state of the MMD matching the common state for the MMD.

A pulse-frequency control circuit includes: a selection circuit that receives, and selects from among, a plurality of reference clocks whose phases differ from one another and which have a same reference period; a setting register that stores information for identifying a setting period that is in increments of a first duration shorter than the reference period; and a control circuit that causes, based on the information stored in the setting register, the selection circuit to sequentially and repeatedly select, as a determined rising edge, a rising edge occurring at intervals of the setting period from among rising edges of the plurality of reference clocks, in which the selection circuit sequentially and repeatedly generates an output pulse whose rising edge coincides with the determined rising edge selected, to provide an output pulse sequence of the output pulses.

A frequency divider is provided that includes a plurality of latches for dividing an input clock according to an integer frequency divisor N of three or greater. Each latch is coupled to a corresponding pair of logic gates. For each latch, one of the logic gates in the corresponding pair controls a setting of the latch whereas a remaining one of the logic gates in the corresponding pair controls a resetting of the latch. Each latch outputs a pair of overlapping clock signals that are divided in frequency with respect to the input clock and have a 50% duty cycle. Each logic gate processes a pair of the overlapping clock signal and the input clock signal to provide a non-overlapping clock signal of the same frequency of the overlapping clock signals but have a (50/N) % duty cycle.

A frequency divider is provided that includes a plurality of latches for dividing an input clock according to an integer frequency divisor N of three or greater. Each latch is coupled to a corresponding pair of logic gates. For each latch, one of the logic gates in the corresponding pair controls a setting of the latch whereas a remaining one of the logic gates in the corresponding pair controls a resetting of the latch. Each latch outputs a pair of overlapping clock signals that are divided in frequency with respect to the input clock and have a 50% duty cycle. Each logic gate processes a pair of the overlapping clock signal and the input clock signal to provide a non-overlapping clock signal of the same frequency of the overlapping clock signals but have a (50/N) % duty cycle.

Embodiments of the present invention relate to an architecture that uses hierarchical statistically multiplexed counters to extend counter life by orders of magnitude. Each level includes statistically multiplexed counters. The statistically multiplexed counters includes P base counters and S subcounters, wherein the S subcounters are dynamically concatenated with the P base counters. When a row overflow in a level occurs, counters in a next level above are used to extend counter life. The hierarchical statistically multiplexed counters can be used with an overflow FIFO to further extend counter life.

Embodiments of the present invention relate to an architecture that uses hierarchical statistically multiplexed counters to extend counter life by orders of magnitude. Each level includes statistically multiplexed counters. The statistically multiplexed counters includes P base counters and S subcounters, wherein the S subcounters are dynamically concatenated with the P base counters. When a row overflow in a level occurs, counters in a next level above are used to extend counter life. The hierarchical statistically multiplexed counters can be used with an overflow FIFO to further extend counter life.

Aspects of the disclosure are directed to multi-module frequency division. As may be implemented in accordance with one or more embodiments herein, an apparatus includes latching circuitry having three or fewer vertically-stacked transistors between power rails, which operate to provide output signals from input signals, the output signals having a frequency that is a divided representation of the frequency of the input signals. A pulse widening circuit modifies the output signals by widening a pulse thereof, providing a modified output signal. A further latching circuit may be utilized to perform a further frequency division of the modified output signal. The respective latching circuitry can be used to selectively provide frequency-divided output signals from input signals at respective divided frequencies.