A pulse-frequency control circuit includes: a selection circuit that receives, and selects from among, a plurality of reference clocks whose phases differ from one another and which have a same reference period; a setting register that stores information for identifying a setting period that is in increments of a first duration shorter than the reference period; and a control circuit that causes, based on the information stored in the setting register, the selection circuit to sequentially and repeatedly select, as a determined rising edge, a rising edge occurring at intervals of the setting period from among rising edges of the plurality of reference clocks, in which the selection circuit sequentially and repeatedly generates an output pulse whose rising edge coincides with the determined rising edge selected, to provide an output pulse sequence of the output pulses.

A setting data output circuit (3) is configured to update setting data in synchronization with a frequency divided signal output from a dual modulus frequency divider on a last stage out of the dual modulus frequency dividers to which a non-significant reset signal is output from a reset circuit (6) which are included in a plurality of dual modulus frequency dividers (1-1 and 1-2) in a first frequency divider group (1). As a result, when a frequency dividing ratio of the dual modulus frequency divider on the last stage out of valid dual modulus frequency dividers contributing to frequency dividing operation is 3, it is possible to realize normal frequency dividing operation even in a case in which frequency dividing ratio setting data to decrease the number of valid dual modulus frequency dividers contributing to the frequency dividing operation is provided.

A setting data output circuit (3) is configured to update setting data in synchronization with a frequency divided signal output from a dual modulus frequency divider on a last stage out of the dual modulus frequency dividers to which a non-significant reset signal is output from a reset circuit (6) which are included in a plurality of dual modulus frequency dividers (1-1 and 1-2) in a first frequency divider group (1). As a result, when a frequency dividing ratio of the dual modulus frequency divider on the last stage out of valid dual modulus frequency dividers contributing to frequency dividing operation is 3, it is possible to realize normal frequency dividing operation even in a case in which frequency dividing ratio setting data to decrease the number of valid dual modulus frequency dividers contributing to the frequency dividing operation is provided.

A setting data output circuit (3) is configured to update setting data in synchronization with a frequency divided signal output from a dual modulus frequency divider on a last stage out of the dual modulus frequency dividers to which a non-significant reset signal is output from a reset circuit (6) which are included in a plurality of dual modulus frequency dividers (1-1 and 1-2) in a first frequency divider group (1). As a result, when a frequency dividing ratio of the dual modulus frequency divider on the last stage out of valid dual modulus frequency dividers contributing to frequency dividing operation is 3, it is possible to realize normal frequency dividing operation even in a case in which frequency dividing ratio setting data to decrease the number of valid dual modulus frequency dividers contributing to the frequency dividing operation is provided.

A clock signal frequency divider according to one aspect of the present disclosure includes: an output signal generation circuit configured to generate, from pulses of a received input clock signal, an output clock signal including a repetition of a periodic pattern signal in which a pulse of a mask pulse number is masked among consecutive pulses of a periodic pulse number, the periodic pattern signal including a marker portion including at least one unmasked pulse at a start portion of the periodic pattern signal; and an output circuit configured to output the output clock signal, wherein the output signal generation circuit generates the periodic pattern signal in such a way that a pattern of a timing of the at least one unmasked pulse of the marker portion does not appear in a portion other than a portion corresponding to the marker portion in the output clock signal.

A clock signal frequency divider according to one aspect of the present disclosure includes: an output signal generation circuit configured to generate, from pulses of a received input clock signal, an output clock signal including a repetition of a periodic pattern signal in which a pulse of a mask pulse number is masked among consecutive pulses of a periodic pulse number, the periodic pattern signal including a marker portion including at least one unmasked pulse at a start portion of the periodic pattern signal; and an output circuit configured to output the output clock signal, wherein the output signal generation circuit generates the periodic pattern signal in such a way that a pattern of a timing of the at least one unmasked pulse of the marker portion does not appear in a portion other than a portion corresponding to the marker portion in the output clock signal.

Embodiments of the present invention relate to an architecture that uses hierarchical statistically multiplexed counters to extend counter life by orders of magnitude. Each level includes statistically multiplexed counters. The statistically multiplexed counters includes P base counters and S subcounters, wherein the S subcounters are dynamically concatenated with the P base counters. When a row overflow in a level occurs, counters in a next level above are used to extend counter life. The hierarchical statistically multiplexed counters can be used with an overflow FIFO to further extend counter life.

Embodiments of the present invention relate to an architecture that uses hierarchical statistically multiplexed counters to extend counter life by orders of magnitude. Each level includes statistically multiplexed counters. The statistically multiplexed counters includes P base counters and S subcounters, wherein the S subcounters are dynamically concatenated with the P base counters. When a row overflow in a level occurs, counters in a next level above are used to extend counter life. The hierarchical statistically multiplexed counters can be used with an overflow FIFO to further extend counter life.

Frequency divider techniques are disclosed which can be used to address two problems: when an incorrect division occurs if the modulus control changes before the divide cycle is complete, and when an incorrect division occurs due to a boundary crossing (e.g., power-of-2 boundary crossing in a fractional-N PLL application). In one embodiment, a frequency divider is provided comprising a plurality of flip-flops operatively coupled to carry out division of an input frequency, and configured to generate a modulus output and receive a divided clock signal of a previous cell. An additional flip-flop is selectively clocked off one of the modulus output or the divided clock of the previous stage, depending at least in part on a Skip control signal applied to a data input of the additional flip-flop, and is further configured to selectively reset the plurality of flip-flops to a state that will result in a correct divide ratio.

Systems and methods for dividing input clock signals by programmable divide ratios can produce output clock signals with the delay from the input clock signal to the output clock signal independent of the value of the divide ratio and with the duty cycle of the output clock signal being 50% independent of the value of the divide ratio. An example programmable clock divider includes a modulo N counter that produces a count signal that counts modulo the divide ratio and a half-rate clock signal generator that produces a common half-rate clock signal, an even half-rate clock signal, and an odd half-rate clock signal that toggle at one-half the rate of the output clock signal. The common half-rate clock signal, the even half-rate clock signal, and the odd half-rate clock signal are combined to produce the output clock signal.