Systems and methods for dividing input clock signals by programmable divide ratios can produce output clock signals with the delay from the input clock signal to the output clock signal independent of the value of the divide ratio and with the duty cycle of the output clock signal being 50% independent of the value of the divide ratio. An example programmable clock divider includes a modulo N counter that produces a count signal that counts modulo the divide ratio and a half-rate clock signal generator that produces a common half-rate clock signal, an even half-rate clock signal, and an odd half-rate clock signal that toggle at one-half the rate of the output clock signal. The common half-rate clock signal, the even half-rate clock signal, and the odd half-rate clock signal are combined to produce the output clock signal.

Embodiments of the present invention relate to an architecture that uses hierarchical statistically multiplexed counters to extend counter life by orders of magnitude. Each level includes statistically multiplexed counters. The statistically multiplexed counters includes P base counters and S subcounters, wherein the S subcounters are dynamically concatenated with the P base counters. When a row overflow in a level occurs, counters in a next level above are used to extend counter life. The hierarchical statistically multiplexed counters can be used with an overflow FIFO to further extend counter life.

Embodiments of the present invention relate to an architecture that uses hierarchical statistically multiplexed counters to extend counter life by orders of magnitude. Each level includes statistically multiplexed counters. The statistically multiplexed counters includes P base counters and S subcounters, wherein the S subcounters are dynamically concatenated with the P base counters. When a row overflow in a level occurs, counters in a next level above are used to extend counter life. The hierarchical statistically multiplexed counters can be used with an overflow FIFO to further extend counter life.

A pulse signal generator has an input receiving an initial pulse signal having an initial period, an oscillator generating an oscillator signal, a first stage and a second stage. The first stage is synchronized with the oscillator signal and configured to deliver a secondary pulse signal having a separation between successive pulses that is representative of an integer part of a division of the initial period by an integer N. The first stage further delivers an auxiliary signal representative of a fractional part of the division and containing, for each pulse of the secondary pulse signal, an indication of a time shift to be applied to the pulse taking into account the separation. The second stage is configured to receive the successive pulses and the corresponding time shift indications and generate successive corresponding pulses of an output pulse signal.

Systems and methods for dividing input clock signals by programmable divide ratios can produce output clock signals with the delay from the input clock signal to the output clock signal independent of the value of the divide ratio and with the duty cycle of the output clock signal being 50% independent of the value of the divide ratio. An example programmable clock divider includes a modulo N counter that produces a count signal that counts modulo the divide ratio and a half-rate clock signal generator that produces a common half-rate clock signal, an even half-rate clock signal, and an odd half-rate clock signal that toggle at one-half the rate of the output clock signal. The common half-rate clock signal, the even half-rate clock signal, and the odd half-rate clock signal are combined to produce the output clock signal.

An input value, where the input value is an amount which the current value of the counter is to be increased is received. The current value of the modulo binary counter and an offset value of the modulo binary counter are increased by the input value. Whether the current value of the counter is greater than or equal to the modulus value of the binary counter is determined. The current value of the counter is replaced with an updated offset value of the counter, where the updated offset value is the offset value of the counter increased by the input value. The updated offset value of the counter is returned.

A computational pixel imaging device that includes an array of pixel integrated circuits for event-based detection and imaging. Each pixel may include a digital counter that accumulates a digital number, which indicates whether a change is detected by the pixel. The counter may count in one direction for a portion of an exposure and count in an opposite direction for another portion of the exposure. The imaging device may be configured to collect and transmit key frames at a lower rate, and collect and transmit delta or event frames at a higher rate. The key frames may include a full image of a scene, captured by the pixel array. The delta frames may include sparse data, captured by pixels that have detected meaningful changes in received light intensity. High speed, low transmission bandwidth motion image video can be reconstructed using the key frames and the delta frames.

A method for creating and transmitting an encoded data stream comprises receiving a data stream that includes a number M of same-rate data streams x.sub.1, x.sub.2, . . . , x.sub.M, where each data stream in the M same-rate data streams has an ordered number of bits with each bit having a period of T.sub.sym and a clock pulse signal that includes a plurality of pulses where a time duration of each pulse in the plurality of pulses corresponds to T.sub.sym/M. A number M of pulse signals is generated, and an encoded data stream is created by multiplying a value of one bit of each data stream in the ordered number M of data streams by a value of a corresponding of a pulse signal in the ordered number M of orthogonal pulse signals to provide M results, and summing the M results. Once summed, the encoded data stream can be transmitted.

A method for creating and transmitting an encoded data stream comprises receiving a data stream that includes a number M of same-rate data streams x.sub.1, x.sub.2, . . . , x.sub.M, where each data stream in the M same-rate data streams has an ordered number of bits with each bit having a period of T.sub.sym and a clock pulse signal that includes a plurality of pulses where a time duration of each pulse in the plurality of pulses corresponds to T.sub.sym/M. A number M of pulse signals is generated, and an encoded data stream is created by multiplying a value of one bit of each data stream in the ordered number M of data streams by a value of a corresponding of a pulse signal in the ordered number M of orthogonal pulse signals to provide M results, and summing the M results. Once summed, the encoded data stream can be transmitted.

A method for creating and transmitting an encoded data stream comprises receiving a data stream that includes a number M of same-rate data streams x.sub.1, x.sub.2, . . . , x.sub.M, where each data stream in the M same-rate data streams has an ordered number of bits with each bit having a period of T.sub.sym and a clock pulse signal that includes a plurality of pulses where a time duration of each pulse in the plurality of pulses corresponds to T.sub.sym/M. A number M of pulse signals is generated, and an encoded data stream is created by multiplying a value of one bit of each data stream in the ordered number M of data streams by a value of a corresponding of a pulse signal in the ordered number M of orthogonal pulse signals to provide M results, and summing the M results. Once summed, the encoded data stream can be transmitted.