A multiplier circuit can be fabricated within an integrated circuit and can draw a product output node to a voltage proportional to a product of first and second binary numbers received at two sets of inputs. The multiplier circuit includes a set of scaled capacitors, each capacitor of the set connected to an output of a multiplexor and to a local product output node. Each multiplexor is connected to the output of a multiplexor configured to generate an analog voltage in proportion to the value of the first binary number. Each scaled capacitor has a capacitance proportional to a significance of a respective bit of the second binary number. The multiplier circuit includes a reference capacitor connected to ground and the product output node, and a reset circuit configured to draw, in response to a RESET signal, the product output node to ground.

A counter can have a number of sensing components. Each respective sensing component can be configured to sense a respective event and can include a respective first capacitor configured to be selectively coupled to a second capacitor in response to the respective sensing component sensing the respective event. The second capacitor can be configured to be charged to a voltage by each respective first capacitor that is selectively coupled to the second capacitor. The counter can have a comparator with a first input coupled to the second capacitor and a second input coupled to a reference voltage corresponding to a threshold quantity of events. The comparator can be configured to output a signal indicative of the threshold quantity of events being sensed in response to the voltage of the second capacitor being greater than or equal to the reference voltage.

A multiplier circuit can be fabricated within an integrated circuit and can draw a product output node to a voltage proportional to a product of first and second binary numbers received at two sets of inputs. The multiplier circuit includes a set of scaled capacitors, each capacitor of the set connected to an output of a multiplexor and to a local product output node. Each multiplexor is connected to the output of a multiplexor configured to generate an analog voltage in proportion to the value of the first binary number. Each scaled capacitor has a capacitance proportional to a significance of a respective bit of the second binary number. The multiplier circuit includes a reference capacitor connected to ground and the product output node, and a reset circuit configured to draw, in response to a RESET signal, the product output node to ground.

The disclosure provides a light emitting diode including a light emitting diode (LED), a first transistor, a second transistor and capacitor. A cathode terminal of the LED is configured to receive a first power supply voltage. A first port of the capacitor coupled to the gate of the first transistor is configured to store a data signal in a first duration. A first port of the second transistor is configured to receive a second power supply voltage. A gate of the second transistor is configured to receive a PWM signal in a second duration. A second port of the second transistor is coupled to the second port of the first transistor. The second transistor is turned on for a conducting time in the second duration according to the PWM signal, and the first transistor provides, in the conducting time, a drive current to the LED according to the data signal.

The disclosure provides a light emitting diode including a light emitting diode (LED), a first transistor, a second transistor and capacitor. A cathode terminal of the LED is configured to receive a first power supply voltage. A first port of the capacitor coupled to the gate of the first transistor is configured to store a data signal in a first duration. A first port of the second transistor is configured to receive a second power supply voltage. A gate of the second transistor is configured to receive a PWM signal in a second duration. A second port of the second transistor is coupled to the second port of the first transistor. The second transistor is turned on for a conducting time in the second duration according to the PWM signal, and the first transistor provides, in the conducting time, a drive current to the LED according to the data signal.

A micro-electromechanical system (MEMS) frequency divider apparatus having one or more MEMS resonators on a substrate is presented. A first oscillator frequency, as an approximate multiple of the parametric oscillation frequency, is capacitively coupled from a very closely-spaced electrode (e.g., 40 nm) to a resonant structure of the first oscillator, thus inducing mechanical oscillation. This mechanical oscillation can be coupled through additional MEMS resonators on the substrate. The mechanical resonance is then converted, in at least one of the MEMS resonators, by capacitive coupling back to an electrical signal which is a division of the first oscillation frequency. Output may be generated as a single ended output, or in response to a differential signal between two output electrodes.

A micro-electromechanical system (MEMS) frequency divider apparatus having one or more MEMS resonators on a substrate is presented. A first oscillator frequency, as an approximate multiple of the parametric oscillation frequency, is capacitively coupled from a very closely-spaced electrode (e.g., 40 nm) to a resonant structure of the first oscillator, thus inducing mechanical oscillation. This mechanical oscillation can be coupled through additional MEMS resonators on the substrate. The mechanical resonance is then converted, in at least one of the MEMS resonators, by capacitive coupling back to an electrical signal which is a division of the first oscillation frequency. Output may be generated as a single ended output, or in response to a differential signal between two output electrodes.

Circuits and methods for determining a majority vote from a plurality of inputs. An example circuit includes a voting input stage, a transfer stage, and an accumulating stage. The voting input stage includes at least three input switched capacitors. The transfer stage includes transfer switched capacitors corresponding to the input switched capacitors. The transfer switched capacitors charge a voting capacitor corresponding to each input switched capacitor during a state of a clock signal. The accumulating stage includes accumulating switched capacitors connecting the voting capacitors in series. The accumulating switched capacitors cause the charges of the voting capacitors to be accumulated during an alternate state of the clock signal. The accumulated charge of the voting capacitors represents a majority vote of the input switched capacitors.

Systems and methods for trusted integration of untrusted components. An example system includes at least three electrical components and voting (consensus) circuitry. The components have varied hierarchical implementations for providing common output given common input. The voting circuitry is configured to receive, as input, outputs from the components and provide a consensus output that is a majority of the outputs received from the components. Such a diversity of multiple untrusted system components (hardware and/or software) engaged in redundant operation can be integrated to as a consensus-based trusted system with a high degree of fault tolerance to unforeseen environmental interference, cyber-attack, supply chain counterfeit, inserted Trojan logic, or component design flaws. The degree of fault tolerance can be increased by increasing the degree of diversity of redundant operational nodes or by increasing the number of diversely implemented operational nodes.

Circuits and methods for determining a majority vote from a plurality of inputs. An example circuit includes a voting input stage, a transfer stage, and an accumulating stage. The voting input stage includes at least three input switched capacitors. The transfer stage includes transfer switched capacitors corresponding to the input switched capacitors. The transfer switched capacitors charge a voting capacitor corresponding to each input switched capacitor during a state of a clock signal. The accumulating stage includes accumulating switched capacitors connecting the voting capacitors in series. The accumulating switched capacitors cause the charges of the voting capacitors to be accumulated during an alternate state of the clock signal. The accumulated charge of the voting capacitors represents a majority vote of the input switched capacitors.