A bridge rectifier and associated control circuitry collectively form a “regtifier” which rectifies an input time varying voltage and regulates the rectified output voltage produced without the use of a traditional voltage regulator. To accomplish this, the gate voltages of transistors of the bridge rectifier that are on during a given phase may be modulated via analog control (to increase the on-resistance of those transistors) or via pulse width modulation (to turn off those transistors prior to the end of the phase). The transistors of the bridge rectifier that would otherwise be off during a given phase may be turned on to help dissipate excess power and thereby regulate the output voltage. This modulation is based upon both a voltage feedback signal and a current feedback signal.

Systems, methods, techniques and apparatuses of power switches are disclosed. One exemplary embodiment is a power switch comprising a first semiconductor device and a second semiconductor device coupled together in a first anti-series configuration between a first terminal and a second terminal; a third semiconductor device and a fourth semiconductor device coupled together in a second anti-series configuration between the first terminal and the second terminal; a controller configured to operate the power switch to simultaneously conduct a first portion of a load current from the first terminal to the second terminal by closing the first semiconductor device and the second semiconductor device, and to conduct a second portion of the load current from the first terminal to the second terminal by closing the third semiconductor device and the fourth semiconductor device.

Disclosed herein is a bridge rectifier and associated control circuitry collectively forming a “regtifier”, capable of both rectifying an input time varying voltage as well as regulating the rectified output voltage produced. To accomplish this, the gate voltages of transistors of the bridge rectifier that are on during a given phase may be modulated via analog control (to increase the on-resistance of those transistors) or via pulse width modulation (to turn off those transistors prior to the end of the phase). Alternatively or additionally, the transistors of the bridge rectifier that would otherwise be off during a given phase may be turned on to help dissipate excess power and thereby regulate the output voltage. A traditional voltage regulator, such as a low-dropout amplifier, is not used in this design.

A semiconductor device includes a first terminal for a battery, a second terminal for an inverter circuit, and a transistor. The semiconductor device is configured to control a voltage applied to a control terminal of the transistor to allow supply of a current from the first terminal to the second terminal and allow supply of a current from the second terminal to the first terminal. A withstand voltage between the first terminal and the second terminal is greater than or equal to a voltage between the battery and the inverter circuit.

Bus bars are soldered to a wiring pattern of a printed board to which the bus bars are connected, and the bus bars are screwed to the printed board. Tips of bolts passing through holes in the bus bars and holes in the punted board may be tightened using nuts. The holes in the printed board may be electrically connected to the wiring pattern.

A switch comprising: a channel path comprising first and second MOS transistors with common source and gate terminals and drain terminals defining first and second terminals of the channel path; and control circuitry comprising: a third MOS transistor comprising: a gate coupled to the common source terminal; a source coupled to the common gate terminal by a resistor; and a drain coupled to a first reference terminal; a first current source coupled between the first reference terminal and the common gate terminal for providing a first current; a second current source coupled between the source terminal of the third MOS transistor and a second reference terminal for providing a second current greater than the first current; and a first switching arrangement configured to selectively enable and disable the first current source; and a second switching arrangement configured to selectively couple the common source terminal to the second reference terminal.

A positive-logic FET switch stack that does not require a negative bias voltage, exhibits high isolation and low insertion/mismatch loss, and may withstand high RF voltages. Embodiments include a FET stack comprising series-coupled positive-logic FETs (i.e., FETs not requiring a negative voltage supply to turn OFF), series-coupled on at least one end by an “end-cap” FET of a type that turns OFF when its V.sub.GS is zero volts. The one or more end-cap FETs provide a selectable capacitive DC blocking function or a resistive signal path. Embodiments include a stack of FETs of only the zero V.sub.GS type, or a mix of positive-logic and zero V.sub.GS type FETs with end-cap FETs of the zero V.sub.GS type. Some embodiments withstand high RF voltages by including combinations of series or parallel coupled resistor ladders for the FET gate resistors, drain-source resistors, body charge control resistors, and one or more AC coupling modules.

A semiconductor device includes a first terminal for a battery, a second terminal for an inverter circuit, and a transistor. The semiconductor device is configured to control a voltage applied to a control terminal of the transistor to allow supply of a current from the first terminal to the second terminal and allow supply of a current from the second terminal to the first terminal. A withstand voltage between the first terminal and the second terminal is greater than or equal to a voltage between the battery and the inverter circuit.

The disclosure relates to a switch arrangement for a converter, comprises: a first series connection of at least two switches between two terminals of the switch arrangement, wherein the two switches are semiconductor switches; a second series connection of a first capacitor and a first diode circuit electrically connected in parallel to first part of the first series connection between a first terminal of the two terminals and node between the two switches, wherein the first diode circuit comprises at least one diode; and third series connection of a second capacitor and a second diode circuit electrically connected in parallel to a second part of the first series connection between second terminal of the two terminals and the node between the two switches, wherein the second diode circuit comprises at least one diode. Further a method for switching such a switch arrangement between the conducting state and the non-conducting state.

In one aspect, a solid-state switching apparatus is provided that includes a pair of anti-parallel thyristors, a quasi-resonant turn-off circuit, a sensor, and a control circuit. The turn-off circuit is coupled in parallel with the pair of anti-parallel thyristors and includes a first selectively conductive path and a second selectively conductive path. The sensor is configured to sense a thyristor current conducted by at least one of the pair of anti-parallel thyristors. The control circuit is configured to receive the sensed thyristor current from the sensor and determine a magnitude of the sensed thyristor current and a polarity of the sensed thyristor current. The control circuit is further configured to activate, in response to determining that the magnitude is greater than a threshold value, one of the first selectively conductive path and the second selectively conductive path based on the polarity to commutate and interrupt the thyristor current.