A radio frequency switch device includes a first transistor and a second transistor; a compensation network coupled between a body terminal of the first transistor and a source/drain terminal of the second transistor; and a bootstrapping network having a first terminal coupled to a first bias terminal, a second terminal coupled to a gate terminal of the first transistor, and a third terminal coupled to the body terminal of the first transistor, wherein the bootstrapping network establishes a low impedance path between the gate terminal and the body terminal of the first transistor in response to a first voltage value of the first bias terminal, and wherein the bootstrapping network establishes a high impedance path between the gate terminal and the body terminal of the first transistor in response to a second voltage value of the first bias terminal.

A power supply switching circuit that selects one power supply potential from among a plurality of power supply potentials. This power supply switching circuit is provided with a transistor QP1 that is connected between an input node N1 and node N2 and has a back gate connected to node N1, a transistor QP2 that is connected between node N2 and output node N3 and has a back gate connected to node N3, a transistor QP3 that is connected between input node N4 and node N5 and has a back gate connected to node N4, a transistor QP4 that is connected between the node N5 and N3 and has a back gate connected to node N3, and a control signal generation unit that sets a group of transistors QP1 and QP2 and a group of transistors QP3 and QP4 to a conduction state and sets the other to a non-conduction state.

A monolithically integrated semiconductor switch, particularly a circuit breaker, has regenerative turn-off behaviour. The semiconductor switch has two monolithically integrated field effect transistors, for example a p-JFET and a n-JFET. The source electrodes of both JFETs and the well region of the n-JFET are short circuited. In addition, the gate electrodes of both JFETs and the drain electrode of the p-JFET are short-circuited via the cathode. In contrast, the well region of the p-JFET is short-circuited to the anode. In this way, a monolithically integrated semiconductor switch is created which turns off automatically when a certain anode voltage level or a certain anode current level is exceeded. The threshold values for the anode voltage and the anode current can be set by appropriate dimensioning of the elements. In this way, it is possible to achieve blocking strengths of up to 200 kV with fast response behaviour.

A semiconductor integrated circuit includes an output circuit driven by a power voltage across a first and a second node. A control circuit is driven by the power voltage to control output a digital signal at a pad terminal, a logic value of the signal being set by a core circuit connected to the output circuit. The digital signal causes a voltage at the first node to be high and a voltage at the second node to low when a predetermined power voltage higher than a withstanding voltage of the output circuit is applied across the first and second nodes. The control circuit controls voltages across terminals of switching elements in the output circuit to be less than their withstanding voltages and to prevent current flowing from the pad terminal to the output circuit when the first power node is in a high impedance state.

A load driving method includes bringing an output transistor disposed between a first power supply line and an output terminal connected to a load into a conduction state by a protection transistor provided between a gate of the output transistor and a second power supply line when a polarity of a power supply coupled between the first power supply line and the second power supply lines is reversed, and forming a conductive path between the second power supply line and a back gate of the protection transistor via a transistor by a back gate control circuit when the polarity of the power supply is normal, the back gate control circuit including the transistor, a gate of the transistor being coupled to the first power supply line directly via a connection node located in a connecting line that couples the first power supply line and the output transistor, the transistor being coupled between the second power supply line and the back gate of the protection transistor.

An apparatus is provided which comprises: a bi-directional switch; and a comparator coupled to the bi-directional switch, the comparator having: a first input coupled to a first terminal of the bi-directional switch; a second input coupled to a second terminal of the bi-directional switch; and an output coupled to a body or substrate of the bi-directional switch.

In one example, a circuit includes a switching unit including a first node, a second node, a control node, and a body. The switching unit is configured to selectively couple the first node of the switching unit to the second node of the switching unit in response to receiving a control signal at a control input of the switching unit. The circuit further includes a reverse current protection unit configured to reduce a current flow from the second node of the switching unit to the first node of the switching unit. The reverse current protection unit selectively couples the first node of the switching unit and the body of the switching unit and selectively couples the second node of the switching unit to the body of the switching unit.

An output driver (1) comprises a driver transistor (MP0) having a gate node (GMP0) to apply a gate control voltage (GCV) and a gate control circuit (30) to control the gate node (GMP0) of the driver transistor (MP0). The output driver (1) is configured to be operable in a first operation mode and a second operation mode, the variable resistance of the current path of the driver transistor (MP0) being lower in the first operation mode than in the second operation mode. The gate control circuit (30) comprises a controllable resistor (RC), the controllable resistor (RC) being disposed between the gate node (GMP0) of the driver transistor (MP0) and an output node (QP) of the output driver (1), and a resistance of the controllable resistor (RC) being dependent on operating the output driver in the first or second operation mode.

The present description concerns a comparator (1) of a first voltage (V+) and of a second voltage (V−), comprising first (100) and second (102) branches each comprising a same succession of alternated first (106) and second (108) gates in series between a node (104) and an output (1002; 1022) of the branch (100; 102), wherein: each branch starts with a first gate (106), each gate (106; 108) has a second node (114) receiving a bias voltage, the second node (114) of each first gate (106) of the first branch (100) and of each second gate (108) of the second branch (102) receives the first voltage (V+), the second node of the other gates receiving the second voltage (V−), and an order of arrival of the edges on the outputs (1002; 1022) of the branches determines a result of a comparison.

An output driver (1) comprises a driver transistor (MP0) having a gate node (GMP0) to apply a gate control voltage (GCV) and a gate control circuit (30) to control the gate node (GMP0) of the driver transistor (MP0). The output driver (1) is configured to be operable in a first operation mode and a second operation mode, the variable resistance of the current path of the driver transistor (MP0) being lower in the first operation mode than in the second operation mode. The gate control circuit (30) comprises a controllable resistor (RC), the controllable resistor (RC) being disposed between the gate node (GMP0) of the driver transistor (MP0) and an output node (QP) of the output driver (1), and a resistance of the controllable resistor (RC) being dependent on operating the output driver in the first or second operation mode.