A switching circuit has a primary MOSFET switch connected between first and second terminals that are connected to a power line and a load represented as a resistance and inductance. The primary switch is operable by primary control commands to assume a conductive or non-conductive state. Four protection branches are connected in parallel with the primary switch, each having a series connected resistive element and a secondary MOSFET switch operable by branch control commands received at branch command terminals to assume a conductive or non-conductive state. A timing circuit applies branch turn off control commands in sequence to the branch command terminals, each delayed by a different predetermined time interval relative to when a primary turn off control command is applied to the primary switch.

A closed loop switch control system and a corresponding method is provided for controlling an impedance of a switch. The switch, which usually comprises a transistor switch, may be part of an external circuit. The system comprises the switch and a control unit coupled to the switch. The control unit is configured to regulate an impedance of the switch to a reference impedance while also enabling a fast switch response time. This is achieved by configuring the control unit to have a frequency response comprising a plurality of dominant poles and at least one zero.

Systems, apparatuses, and methods for efficient operation of a switch arrangement are described. Selectively operating one of a plurality of parallel-connected switches at different times along a period of a periodic waveform may allow for improved efficiency, uniform loss-spreading, and enhanced thermal design of an electronic circuit including use of power switches.

Circuits and methods for controlling a transistor that has first, second and third terminals, wherein a voltage level at said first terminal controls in part a current flow from said second terminal to said third terminal. A controller receives an voltage existing across the second and third terminals of the transistor, generates an isolated voltage and uses that voltage to power components of the controller. The controller provides a voltage to the first terminal of the transistor, whereby the controller regulates the voltage across the second and third terminals of the transistor by regulating the voltage provided to the first terminal.

According to one embodiment, a current detecting circuit includes: a normally-ON type first switching element that includes a drain, a source, and a gate; a normally-OFF type second switching element including a drain that is connected to the source of the first switching element, a source that is connected to the gate of the first switching element, and a gate; and a differential amplification circuit that outputs a voltage according to a voltage between the drain and the source of the second switching element.

A switch device includes a switching element that connects/disconnects a current path from a power supply terminal to a ground terminal via a load, and an overcurrent protection circuit that limits output current flowing in the switching element to be an overcurrent limit value or less. When an output short circuit of the load is detected, the overcurrent protection circuit decreases the overcurrent limit value to be lower as a power supply voltage is higher. In addition, the switch device preferably includes a switching element that connects/disconnects a current path from a power supply terminal to a ground terminal via a load, an intermittent control unit that intermittently drives the switching element when an abnormality is detected, and an output voltage monitoring portion that disables the intermittent control unit until an output voltage applied to the load reaches its target value.

An integrated circuit is provided with an MCU, which is configured to generate a PWM control signal that is free of switching pattern information therein. A current-estimating gate driver is provided, which is responsive to the PWM signal. This gate driver is configured to drive first and second gate terminals of first and second parallel switching devices (within a hybrid switch) with gate signals that establish a second switching pattern within the hybrid switch. These gate driving operations are performed in response to measuring a first voltage associated with a terminal of the hybrid switch when being driven by gate signals that establish a first switching pattern within the hybrid switch that is different from the second switching pattern. The duty cycles of the gate signals associated with the second switching pattern are unequal and the duty cycles of the gate signals associated with the first switching pattern are unequal.

A one-direction conduction device includes a first transistor and a driving circuit. The first transistor has a control terminal coupled to a first node, and input and output terminals respectively coupled to input and output electrode terminals of the one-direction conduction device. In the driving circuit, a switch circuit is coupled to the input electrode terminal and a second node. A second transistor has a base and a collector both coupled to a third node, and an emitter coupled to the second node. A first resistor is coupled to the third node and ground. A third transistor has a base coupled to the third node, an emitter coupled to the output electrode terminal, and a collector coupled to the first node. The second resistor is coupled between the first node and the ground. The switch circuit breaks off a reverse leakage current path of the one-direction conduction device.

A biasing circuit for a flyback converter can include a rectifier electrically coupled to an inductor of the flyback converter for generating a direct current signal from an alternating current signal outputted by the inductor in response to the inductor transferring an amount of energy to another inductor. The biasing circuit can also include a storage device electronically coupled to the rectifier to receive the direct current signal and store a charge. The biasing circuit can further include a limiting device electronically coupled to the storage device to provide an amount of the charge that is stored in the storage device to an input lead of a switch of the flyback converter for biasing the switch.

A load driving method includes bringing an output transistor disposed between a first power supply line and an output terminal connected to a load into a conduction state by a protection transistor provided between a gate of the output transistor and a second power supply line when a polarity of a power supply coupled between the first power supply line and the second power supply lines is reversed, and forming a conductive path between the second power supply line and a back gate of the protection transistor via a transistor by a back gate control circuit when the polarity of the power supply is normal, the back gate control circuit including the transistor, a gate of the transistor being coupled to the first power supply line directly via a connection node located in a connecting line that couples the first power supply line and the output transistor, the transistor being coupled between the second power supply line and the back gate of the protection transistor.