A DC-to-DC converter is disclosed. The SMPS driver includes a highside switch having a first terminal, a second terminal and a gate. The first terminal is coupled to an input voltage terminal. The SMPS driver further includes a lowside switch having a first terminal, a second terminal and a gate. The first terminal of the lowside switch is coupled to the second terminal of the highside switch and the second terminal of the lowside switch is coupled to ground. A diode is coupled to the gate of the lowside switch on one side and to a capacitor on the other side. An integrated circuit (IC) is included to generate control signals for switching the highside switch and the lowside switch. The IC includes a highside supply pin, a highside gate control pin, a half bridge pin, a lowside gate control pin and a ground pin. The gate of the lowside switch is coupled to the lowside gate control pin, the highside supply pin is coupled to the diode and the capacitor is coupled to the half bridge pin.

Embodiments of the present disclosure include a bidirectional analog switch having a pair of high-voltage transistors coupled together via a common source and gate. The switches are configured to effectively isolate an input terminal from an output terminal by passing leakage and feedthrough to a power supply. In certain embodiments, an off-state pinned switch pins the common source voltage to a power source voltage. A logic circuit receives an input logic signal and generates two non-overlapped output logic signals for controlling the pair of transistors and the off-state pinned switch. In other embodiments, a resistor pins the common source voltage to a power supply voltage for passing leakage and feedthrough to the power supply.

This application relates to methods and apparatus for driving a transducer connected between two output nodes in a bridge-tied-load configuration. A driver receives first and second supply voltages and has charge pumps that generate respective first and second boosted voltages. The driver is operable a first driver mode in which each output node is modulated between the first and second supply voltage; a second driver mode in which one output nodes is modulated between the first and second supply voltages and the other output node is modulated between either the first boosted voltage and the first supply voltage or between the second supply voltage and the second boosted voltage; and a third driver mode in which one of the output nodes is modulated between the first supply voltage and the first boosted voltage and the other output node is modulated between the second supply voltage and the second boosted voltage.

Modulating a gate drive current supplied to an output drive switch coupled to an electric motor by performing at least the following: obtain a gate drive current modulation profile, supply, based on the gate drive current modulation profile, a first gate drive current level as the gate drive current when the output drive switch is operating within a first region, drop the first gate drive current level to a second gate drive current level when the output drive switch transitions from the first region to operating within a Miller region, increase the second gate drive current level to a third gate drive current level within the Miller region, and set the gate drive current to a fourth gate drive current level when the output drive switch transitions from the Miller region to operating within a third region.

A DC-to-DC converter is disclosed. The SMPS driver includes a highside switch having a first terminal, a second terminal and a gate. The first terminal is coupled to an input voltage terminal. The SMPS driver further includes a lowside switch having a first terminal, a second terminal and a gate. The first terminal of the lowside switch is coupled to the second terminal of the highside switch and the second terminal of the lowside switch is coupled to ground. A diode is coupled to the gate of the lowside switch on one side and to a capacitor on the other side. An integrated circuit (IC) is included to generate control signals for switching the highside switch and the lowside switch. The IC includes a highside supply pin, a highside gate control pin, a half bridge pin, a lowside gate control pin and a ground pin. The gate of the lowside switch is coupled to the lowside gate control pin, the highside supply pin is coupled to the diode and the capacitor is coupled to the half bridge pin.

Provided are a semiconductor device and a method of operating the same. A semiconductor device may include a comparator which compares a first voltage with a rectified voltage and provides a second voltage in accordance with the comparison. A timer circuit may operate a timer according to the second voltage and output a third voltage in correspondence with an operation time of the timer. A driver may drive a transistor with a fourth voltage generated by the driver according to the third voltage. A calibration circuit may generate a timer calibration signal based on the second voltage and the fourth voltage. The timer calibration signal may be provided to the timer circuit and used to calibrate the operation time of the timer. More efficient rectification, with reduced occurrence of reverse current, may thereby be realized.

A regenerative current detection circuit includes a first power MOS transistor that is configured as a current mirror to a second power MOS transistor connected to drive a motor winding, a first feedback amplifier that compares a first regenerative current that flows in the first power MOS transistor with a second regenerative current that flows in the second power MOS transistor and outputs a comparison result, the first regenerative current being obtained by multiplying the second regenerative current by a current mirror ratio, and a current detection circuit that outputs a detection current based on the comparison result.

An electric power conversion circuit includes: first through fourth port terminals; a first diode having an anode connected to the first port terminal; a second diode having a cathode connected to the second port terminal; a third diode having a cathode connected to the first port terminal; a fourth diode having an anode connected to the second port terminal; first through fourth switches that are bridge-connected between a cathode of the first diode and an anode of the second diode; fifth through eighth switches that are bridge-connected between an anode of the third diode and a cathode of the fourth diode; a first bootstrap circuit that is connected to control terminals of the first through fourth switches; and a second bootstrap circuit that is connected to control terminals of the fifth through eighth switches.

A drive control device includes a MOS transistor, voltage measuring circuits, a correction circuit, and a control circuit. The voltage measuring circuits measure a drain-to-source voltage when a forward drain current flows through the MOS transistor and when a reverse drain current flows in the MOS transistor. The correction circuit sets a current setting voltage level when the reverse drain current flows, where the current setting voltage level is proportional to the voltage between the drain and the source when a predetermined reverse setting current flows in the MOS transistor. The control circuit controls ON/OFF of the MOS transistor in response to a control signal reflecting a measured value of the first voltage measuring circuit when the forward drain current flows through the MOS transistor and the current setting voltage level that is set by the correction circuit when the reverse drain current flows in the MOS transistor.

A high side transistor is coupled between a high potential side power source node and an intermediate node, and a recirculation diode is coupled between a low potential side power source node and the intermediate node, thereby forming a recirculation path when the high side transistor is OFF. A power source supply line couples the high potential side power source node with one end of the high side transistor. A surge recirculation device causes a current to flow in one direction, and a surge recirculation line couples the one end of the high side transistor to the high potential side power source node through the surge recirculation device, and causes a surge generated at the one end of the high side transistor to recirculate toward the high potential side power source node.