A circuit device includes a regulator, a charge pump circuit, an overvoltage detection circuit, and a control circuit. The regulator regulates a power supply voltage. The charge pump circuit outputs, a gate control voltage, to a gate node of an N-type transistor provided between a power supply node and a load, based on a regulated voltage. The overvoltage detection circuit detects an overvoltage of the regulated voltage. The control circuit controls to stop the charge pump circuit when the overvoltage is detected by the overvoltage detection circuit.

An analog switch circuit includes: a switch unit and a control circuit, wherein the control circuit includes a sensor circuit and a gate-source voltage adjustment circuit. The switch unit operates a first switch therein according to a first gate-source voltage, to convert an input signal of an input terminal to an output signal of an output terminal. The sensor circuit is coupled between the input terminal and the output terminal, and generates a sensing signal according to a voltage difference between the input signal and the output signal. The gate-source voltage adjustment circuit is coupled to the sensor circuit, and adaptively adjusts the first gate-source voltage according to the sensing signal, to maintain the conduction resistance of the switch unit at a constant while the voltage difference changes.

A switch circuit of an embodiment includes a radio-frequency switch and a level shifter circuit. The radio-frequency switch, which includes a first switch group and a second switch group each including a plurality of switches, switches transmission/reception of a radio-frequency signal. The level shifter circuit outputs a first signal for controlling ON/OFF of each switch of the first switch group and a second signal for controlling ON/OFF of each switch of the second switch group.

Disclosed is a switch circuit for an ultra-high frequency band, which includes a transistor including a first terminal connected to an input stage, a second terminal connected to an output stage, and a gate terminal, an inductor connected to the transistor in parallel, between the input stage and the output stage, a variable gate driver to apply a gate input voltage to the gate terminal and, an input resistor connected between the variable gate driver and the gate terminal. The variable gate driver adjusts the gate input voltage to be in one of a first voltage level for turning on the transistor and a second voltage level for turning off the transistor. The second voltage level varies depending on a capacitance between the first terminal and the second terminal, when the transistor is in a turn-off state.

Power supply circuit having low quiescent current for a bypass mode. One example power supply circuit generally includes a transistor; a switching node coupled to a source of the transistor; a power supply rail; a capacitor having a first terminal coupled to the power supply rail and having a second terminal coupled to the switching node; a gate driver having an output coupled to a gate of the transistor, having a first power input coupled to the power supply rail, and having a second power input coupled to the switching node; logic having a first input coupled to the first terminal of the capacitor, having a second input coupled to the second terminal of the capacitor, and having a first output; and a pullup circuit having a control input coupled to a second output of the logic and having an output coupled to the gate of the transistor.

A large-current MOS drive control method, comprising the following steps: 1) turning on a device, initializing the device, activating an MOS switching circuit, and completing a turn-on operation for the circuit; 2) monitoring the voltage connected to the switching circuit, connecting the switching circuit to a power supply after voltage detection, and activating the power supply; 3) connecting the power supply to a control circuit, processing, by the control circuit, information transmitted by the power supply, and driving, by the control circuit, a driving circuit; and 4) after the MOS switching circuit is connected, measuring the temperature of the switching circuit in real time by means of an infrared temperature measurement instrument, and if the temperature exceeds 80 Celsius degrees, giving an alarm by flashing a red alarm lamp.

In some examples, a switch comprises first and second drain-extended transistors of a first type, third and fourth drain-extended transistors of a second type, a switch input coupled between drains of the first and third drain-extended transistors, a switch output coupled between drains of the second and fourth drain-extended transistors, and a control input. The control input is coupled to gates of the first and second drain-extended transistors, a first switch coupled to sources of the first and second drain-extended transistors, a second switch coupled between a voltage supply and gates of the third and fourth drain-extended transistors, and a third switch coupled between the voltage supply and sources of the third and fourth drain-extended transistors. The control input comprises a fifth drain-extended transistor coupled between the sources of the third and fourth drain-extended transistors and the gates of the third and fourth drain-extended transistors.

An apparatus for reducing switching time of RF FET switching devices is described. A FET switch stack includes a stacked arrangement of FET switches and a plurality of gate feed arrangements, each coupled at a different height of the stacked arrangement. A circuital arrangement with a combination of a series RF FET switch and a shunt RF FET switch, each having a stack of FET switches, is also described. The shunt switch has one or more shunt gate feed arrangements with a number of bypass switches that is less than the number of FET switches in the shunt stack.

In some examples, a switch comprises first and second drain-extended transistors of a first type, third and fourth drain-extended transistors of a second type, a switch input coupled between drains of the first and third drain-extended transistors, a switch output coupled between drains of the second and fourth drain-extended transistors, and a control input. The control input is coupled to gates of the first and second drain-extended transistors, a first switch coupled to sources of the first and second drain-extended transistors, a second switch coupled between a voltage supply and gates of the third and fourth drain-extended transistors, and a third switch coupled between the voltage supply and sources of the third and fourth drain-extended transistors. The control input comprises a fifth drain-extended transistor coupled between the sources of the third and fourth drain-extended transistors and the gates of the third and fourth drain-extended transistors.

A high reliability AC load switching circuit is disclosed. In some embodiments, the AC load switching circuit includes a high-speed switch connected between the load and the voltage source, a cutoff switch connected between the load and the voltage source in parallel with the high-speed switch, and a level detector connected to the voltage source and to a control input of the high-speed switch. The high-speed switch may be a solid-state switch, for example, a TRIAC or a bidirectional switch, and the cutoff switch may be an electromechanical switch, for example, a relay. In some embodiments a snubber is connected in parallel with a solid-state switch. In some embodiments a microcontroller is connected to an eletromechanical switch and the level detector. In some embodiments, both a first cutoff switch and a second cutoff switch are used.