The present invention provides a driving circuit for a driving hip. The driving circuit includes a bootstrap circuit with a bootstrap voltage terminal. A power terminal of a high-voltage driving circuit is connected to the bootstrap voltage terminal, and a ground terminal of the high-voltage driving circuit is connected to a regulating terminal. A high-side drive circuit includes a high-side pull-up circuit and a high-side pull-down circuit. The driving circuit includes: an auxiliary power terminal; a mirror current source an input terminal of the mirror current source being connected to the bootstrap voltage terminal; a first MOS transistor; a second MOS transistor an equivalent diode component, an output terminal of the second MOS transistor being connected to the regulating terminal through the equivalent diode component; and an equivalent resistance component, the gate of the first MOS transistor being connected to the regulating terminal through the equivalent resistance component.

A power converter having a slew rate controlling mechanism is provided. A first terminal of a high-side switch is coupled to an input voltage. A first terminal of a low-side switch is connected to a second terminal of the high-side switch. A second terminal of a first capacitor is connected to a node between the second terminal of the high-side switch and the first terminal of the low-side switch. A first terminal of an inductor is connected to the second terminal of the first capacitor and to the node. A first terminal of a second capacitor is connected to a second terminal of the inductor. A second terminal of the second capacitor is grounded. An input terminal of a current controlling device is connected to a power output terminal of a high-side buffer. An output terminal of the current controlling device is connected to the node.

This application discloses a chip and a signal level shifter circuit for use on a mobile terminal such as a charger or an adapter. The chip is co-packaged with a first silicon-based driver die and a second silicon-based driver die that are manufactured by using a BCD technology, and a first gallium nitride die and a second gallium nitride die that are manufactured by using a gallium nitride technology. A first silicon-based circuit is integrated on the first silicon-based driver die, a second silicon-based circuit is integrated on the second silicon-based driver die, and a high-voltage resistant gallium nitride circuit is integrated on the first gallium nitride die. In this way, it can be ensured that a second low-voltage silicon-based driver die manufactured by using a low-voltage BCD technology is not damaged by a high input voltage, thereby reducing costs of the chip.

A signal detection circuit includes: a voltage dividing circuit having at least a first pair of voltage dividing capacitors connected in series for dividing an input voltage and configured to output a divided voltage, and a detection circuit configured to detect the divided voltage. The first pair of voltage dividing capacitors are included in one semiconductor device. The semiconductor device includes: (i) a semiconductor substrate, (ii) a first conductor layer, (iii) a first dielectric layer, (iv) a second conductor layer, (v) a second dielectric layer, (vi) a third conductor layer, and (vii) a short-circuit portion configured to short-circuit the first conductor layer and the semiconductor substrate.

A power supply comprising a first-stage capacitor configured to provide energy to a second stage power converter. An energy transfer element coupled to the first-stage capacitor. A reservoir capacitor coupled to the energy transfer element. The reservoir capacitor is configured to receive charge from the energy transfer element. A power switch configured to control a transfer of energy from an input of the power supply to the first-stage capacitor. A controller coupled to the power switch, the controller configured to generate a hold-up signal in response to the input of the power supply falling below a threshold voltage. A charge circuit comprising a first switch and a second switch configured to be controlled by the hold-up signal. The first switch couples the reservoir capacitor to an input of the energy transfer element. The second switch is configured to uncouple the reservoir capacitor from receiving charge from the energy transfer element.

A driver circuit includes a high side transistor, a low side transistor, a first trigger circuit, and a second trigger circuit. The high side transistor has a first control terminal and a first current path coupled between a first voltage terminal and an output voltage terminal. The low side transistor has a second control terminal and a second current path coupled between the output voltage terminal and ground. The first trigger circuit is coupled to the first control terminal, the first voltage terminal, and the output voltage terminal. The first trigger circuit is operable to protect the high side transistor. The second trigger circuit is coupled to the second control terminal, the first trigger circuit, and ground. The second trigger circuit is operable to protect the low side transistor.

In some examples, this description provides for an apparatus. The apparatus includes a power switch having a power switch source configured to receive an input voltage, a power switch drain, and a power switch gate. The apparatus also includes a current sense component coupled to the power switch. The apparatus also includes a current limiting circuit coupled to the power switch gate, the power switch drain, and the current sense component. The apparatus also includes an over-current protection (OCP) circuit coupled to the power switch source, the power switch drain, and the power switch gate. The apparatus also includes an output voltage (VOUT) clamp coupled to the power switch drain and the power switch gate.

A circuit for detecting a leakage current in a semiconductor element includes a setting circuit and a detector. The semiconductor element includes a first terminal at a high-potential-side of the semiconductor element, a second terminal at a low-potential-side of the semiconductor element, and a control terminal. The control terminal receives a signal for controlling a conduction state between the first terminal and the second terminal. The setting circuit sets a duration during which a charging current flows to the control terminal as an undetectable duration, in response to turning on the semiconductor element. The detector outputs a detected signal based on a condition that the leakage current flowing from the control terminal to the second terminal, after the undetectable duration has been elapsed.

A control unit has an input with a positive and negative connectors. The control unit also includes an output and with an electronic switch. The switch has a first connector, a second connector and a control connector, and has an on-state resistance between its first and second connector that depends on a control voltage at the control connector of the switch. The first connector is connected to the connector for the positive potential of the input, the second connector is connected to the connector for the positive potential of the output, and the control connector is connected to a trigger circuit. A second controllable switch is also included with a first connector connected to the second connector of the first switch, a second connector connected to the control connector of the first switch, and a control connector connected to the connector for the negative potential of the input.

A switching circuit of a motor drive includes a high-side switch configured to selectively conduct current between a DC positive conductor and an output conductor, and a low-side switch configured to selectively conduct current between the output conductor and a DC negative conductor. The high-side switch comprises a depletion mode (D-Mode) gallium nitride (GaN) high-electron-mobility transistor (HEMT) and a Si-FET in a cascaded configuration, and the low-side switch comprises a D-Mode GaN HEMT. This arrangement can provide a safe state operation in which the switching circuit provides a default condition providing electrical continuity between the DC negative conductor and the output conductor and providing electrical isolation between the DC positive conductor and the output conductor in the event of a loss of control signals.