A gate driver, which drives an N-channel type transistor connected between an application terminal of an input voltage and an application terminal of a switch voltage, includes a capacitor circuit connected between an application terminal of a boot voltage higher than the switch voltage by a voltage between both ends of the boot capacitor and the application terminal of the switch voltage, and a timing control circuit that charges an input gate capacitance of the transistor with the boot voltage after precharging the same with the input voltage during turn-on transition of the transistor, and decreases capacitance value of the capacitor circuit after the turn-on transition of the transistor.

In an embodiment, a switching circuit is provided that includes a Group III nitride-based semiconductor body including a first monolithically integrated Group III nitride-based transistor device and a second monolithically integrated Group III nitride based transistor device that are coupled to form a half-bridge circuit and are arranged on a common foreign substrate having a common doping level. The switching circuit is configured to operate the half-bridge circuit at a voltage of at least 300 V.

In a power feeding control device, N-channel first FET and second FET are located in a current path for current flowing from a positive terminal to a negative terminal. The drain of the first FET is located downstream of the source. The drain of the second FET is located upstream of the source. The cathode of a first diode is connected to the negative terminal. A first drive circuit and a second drive circuit switch ON or OFF the first FET and the second FET by adjusting the gates of the first FET and the second FET, with respect to the cathode of the first diode.

A gate driver circuit comprises an auxiliary winding, a voltage summer, an auxiliary voltage bus, a gate driver integrated circuit (IC), and a controller. The auxiliary winding is positioned adjacently to the inductor and configured to inductively couple with the inductor. The voltage summer comprises a pair of diodes coupled to the auxiliary winding and a pair of capacitors coupled to the pair of diodes. The auxiliary voltage bus is configured to receive a summed voltage from the voltage summer based on a sum of voltages stored in the pair of capacitors. The gate driver IC is configured to receive a voltage from a positive rail of the auxiliary voltage bus and to output a gate control signal to control a switching device based on the received voltage and based on a pulse signal generated by the controller.

A drive device includes a driver configured to drive a high-side transistor and a low-side transistor; a first current detecting part for detecting one of an upper-side current that flows to the high-side transistor and a lower-side current that flows to the low-side transistor; a first current determining part that detects a sign of switching of a forward direction/reverse direction of the upper-side current or the lower-side current detected by the first current detecting part or the switching per se; and a slew rate adjusting part configured to control the driver such that a slew rate of the high-side transistor or the low-side transistor is adjusted according to a determination result of the first current determining part.

Detection transistor MNd flows a detection current IdN to a current path CP1n when an output voltage Vo generated in a load terminal PN1 is than a ground voltage GND. A current mirror circuit CMp1 transfers the detection current IdN flowing in the current path CP1n to a current path CP2a. Detecting resistor element Rd1 converts a mirror current I2a flowing in the current path CP2a to a detection voltage Vd1. A control transistor MNc1 is turned on when the converted detection voltage Vd1 is higher than a predetermined value. Then, the output transistor QO is controlled to be off while the control transistor MNc1 is on.

A bootstrap gate driver charging circuit arranged to drive the gate of an upper switch (Q.sub.U) and a lower switch (Q.sub.L) connected in series to provide an AC output voltage (400) voltage by alternatively turning on and off according to a predetermined duty cycle of alternate upper switch turn-on and lower switch turn-on phases, the bootstrap gate driver charging circuit comprising: an input terminal; an output terminal; an H-bridge inverter with an inverter input and an inverter output; a charging path; and a bootstrap capacitor. The input inverter is electrically connected to the input terminal, the inverter output is electrically connected to a first end of the bootstrap capacitor, the charging path is electrically connected between a second end of the bootstrap capacitor and a gate driver supply voltage; wherein in response to the lower switch being turned ON and providing a path to ground with respect to the supply voltage.

A semiconductor device of an embodiment includes: a semiconductor layer having a first face and a second face, the semiconductor layer including a first trench and a second trench on a side of a first face; a first electrode on the side of the first face; a second electrode on the side of the second face; a first gate electrode in the first trench; a first field plate electrode electrically connected to the first electrode in the first trench, a second gate electrode in the second trench; and a second field plate electrode electrically connected to the first electrode in the second trench, a resistance between first electrode and second field plate is different from a resistance between first electrode and the first field plate electrode.

Disclosed is a switch device including a first terminal, a second terminal, a third terminal, a switch element disposed between the first terminal and the second terminal, a control line that reaches a control end of the switch element from the third terminal, a first circuit block that is disposed on the control line and is configured to drive the switch element according to a control signal supplied to the third terminal, at least one second circuit block, each second circuit block being connected to a corresponding one of branch power supply lines that branch from the control line, a first resistor disposed between the third terminal and the first circuit block, and at least one second resistor, each second resistor being disposed on a corresponding one of the branch power supply lines.

Current sensing in an on-die direct current-direct current (DC-DC) converter for measuring delivered power is disclosed. A DC-DC converter converts input voltage to output current at an output voltage coupled to a load circuit. The DC-DC converter includes a high side driver (HSD) circuit to drive the output current in a first stage, and a low side driver (LSD) circuit to couple the power output to a negative supply rail (GND) in a second phase, output current being periodic. The DC-DC converter includes an amplifier circuit to equalize an output voltage and a mirror voltage. Based on the mirror voltage, the current sensing circuit generates mirror current that corresponds to driver current. The mirror current can be measured as a representation of the output current delivered to the load circuit. A plurality of the DC-DC converters can provide multi-phased current to the load circuit for providing power to the load circuit.