The present disclosure concerns a device including a first switch, a diode, and a passive resistive element electrically in series between conduction and control terminals of the first switch, a terminal of the diode located on the side of the first switch being coupled to a node of application of a potential variable with respect to the potential of said conduction terminal.

An integrated circuit includes: a control signal output; a pulse-width modulation (PWM) subsystem with a PWM input and a PWM output, the PWM output configured to provide PWM control signals; and configurable logic (CL) with a first CL input, a second CL input, and a CL output. The first CL input is coupled to the PWM output, the second CL input is adapted to receive a fault indicator. The CL output is coupled to the control signal output. The CL is configured to provide the PWM control signals to the control signal output unless the fault indicator indicates a fault.

A semiconductor device includes: a semiconductor chip; and an Ag fired cap formed so as to cover a source pad electrode formed on the semiconductor chip. The semiconductor chip is disposed on a first substrate electrode, and one end of a Cu wire is bonded onto the Ag fired cap by means of an ultrasonic wave. There is provided a semiconductor device capable of improving a power cycle capability, and a fabrication method of such a semiconductor device.

An electronic device includes a GaN power FET, a GaN driver coupled to the GaN power FET and a gate bias circuit coupled to the GaN driver. The GaN power FET and the GaN driver are monolithically integrated on a single GaN die. The gate bias circuit is predominately monolithically integrated on the single GaN die and includes only one active component external to the single GaN die. In one embodiment, the only active component external to the single GaN die is a linear regulator. In another embodiment, the only active component external to the single GaN die is a shunt regulator. In yet another embodiment, the only active component external to the single GaN die is a Zener diode.

Provided is a semiconductor device comprising a high-side switching device, a low-side switching device, a high-side driver configured to turn on/off the high-side switching device, a low-side driver configured to turn on/off the low-side switching device, a high-side driving external terminal configured to supply a power supply voltage for driving the high-side driver, and a protection circuit section connected to the high-side driving external terminal. The high-side driver may include a reference potential terminal set to a reference potential of the high-side driver. The protection circuit section may be connected between the high-side driving external terminal and the reference potential terminal.

A circuit includes a high-side switch and a low-side switch. A first inverter includes first and second discharge current paths activatable to sink first and second discharge currents, respectively, from the control terminal of the high-side switch. A second inverter includes first and second charge current paths activatable to source first and second charge currents to the control terminal of the low-side switch. A high-side sensing current path includes an intermediate high-side control node, and a low-side sensing current path includes an intermediate low-side control node. The second discharge current path is selectively enablable in response to a high-side detection signal at the intermediate high-side control node having a high logic value, and the second charge current path is selectively enablable in response to a low-side detection signal at the intermediate low-side control node having a low logic value.

A level shifter includes a converter configured to generate a first driving signal and a second driving signal; a current sensing circuit configured to detect a current corresponding to a voltage change of second power, and generate a freezing signal according to the current; a freezing circuit configured to control an operation of the converter according to the freezing signal.

A switching circuit includes a high-side transistor and a low-side transistor, each of which is of an N-channel type. A switch and a rectifying element of a PMOS transistor are provided in series between a constant voltage line through which a constant voltage is supplied and a bootstrap line. A comparison circuit operates using a high-side power supply voltage, which is a potential difference between the bootstrap line and a switching line, as a power supply to generate a detection signal indicating a magnitude relationship between the high-side power supply voltage and a threshold voltage. A level shift circuit level-shifts the detection signal down to a signal of which a ground voltage is low. A PMOS driver drives the switch asynchronously with switching of the low-side transistor in response to an output of the level shift circuit.

A switching method for a half bridge power converter includes at least a pair of power switches in legs of the convertor providing upper and lower branch power switches and first and second gate control circuits for the upper and lower branch power switches. The switching method includes sensing the current derivative in the upper and lower branches during switching of the pair of power switches to provide a first signal and a second signal proportional to the current derivative of the power current in the upper and lower power switches, summing the first and second signals to provide a summed current derivative signal, and adding the summed current derivative signal to the power switch command signal of the first and second gate control circuits causing the summed derivative signals to modulate the gate commutation signals of the gate control circuits.

In an embodiment, a switching circuit is provided that includes a Group III nitride-based semiconductor body including a first monolithically integrated Group III nitride-based transistor device and a second monolithically integrated Group III nitride based transistor device that are coupled to form a half-bridge circuit and are arranged on a common foreign substrate having a common doping level. The switching circuit is configured to operate the half-bridge circuit at a voltage of at least 300V.