Disclosed herein is a power supply circuit for a gate driver. The power supply circuit for the gate driver includes a negative voltage generator configured to generate a negative voltage by receiving an input voltage, wherein the negative voltage generator includes a tank capacitor configured to be charged by receiving the input voltage through a charge path, a discharge switch configured to form a discharge path when the tank capacitor is discharged, and a negative voltage generation capacitor arranged on the discharge path and configured to generate the negative voltage by storing electric charges discharged from the tank capacitor when the tank capacitor is discharged.

Driver circuits to invert an input signal and to generate an output signal based on the inverted input signal are presented. The voltage level of the logical high value of the output signal is adjustable. The driver circuit has a high side switching element coupled between a supply terminal and the output terminal of the driver circuit. The driver circuit has a low side switching element coupled between the output terminal of the driver circuit and a reference potential. The driver circuit has a regulation transistor, wherein a controlled section of the regulation transistor is coupled in series with the high side switching element and the low side switching element between the supply terminal and the reference potential. The driver circuit has a feedback circuit to regulate the output voltage by generating a regulation voltage at a control terminal of the regulation transistor.

A semiconductor device includes: a semiconductor chip; and an Ag fired cap formed so as to cover a source pad electrode formed on the semiconductor chip. The semiconductor chip is disposed on a first substrate electrode, and one end of a Cu wire is bonded onto the Ag fired cap by means of an ultrasonic wave. There is provided a semiconductor device capable of improving a power cycle capability, and a fabrication method of such a semiconductor device.

A system and method for a high-side power switch includes a gate driver configured to be coupled to a power switch, a voltage measurement circuit configured to be coupled directly to the power switch, a switch monitoring circuit configured to be coupled to the power switch, the switch monitoring circuit configured to measure an output current of the power switch, a current limitation circuit coupled to the gate driver and the switch monitoring circuit, the current limitation circuit configured to regulate gate-source voltage of the gate driver when the output current exceeds a threshold value, and a controller coupled to the current limitation circuit and the voltage measurement circuit, the controller configured to determine a mode of operation according to a startup voltage measured by the voltage measurement circuit during a startup sequence, the controller further configured to provide the threshold value to the current limitation circuit according to the mode of operation and a switch voltage measured by the voltage measurement circuit

A semiconductor device includes a power device and a temperature detection diode. The semiconductor device has a device structure configured to insulate between a power lien of the power device and the temperature detection diode.

Provided is a level shift circuit capable of avoiding breakdown due to level shift operation. The level shift circuit includes: a floating power supply having one end connected to an output terminal; a circuit configured to receive a voltage of the floating power supply, a voltage of a low level power supply and first and second pulse signals from a pulse generating circuit, thereof to output first and second signals; and a logic circuit configured to receive first and second signals, thereby converting a signal that is input to the pulse generating circuit into a signal that fluctuates between a voltage at the one end of the floating power supply and a voltage at the other end thereof to output the converted signal.

An integrated circuit includes a die that includes a circuit configured to generate a PWM signal in response to a first clock signal, and a first set of pads configured to provide amplified PWM signals to external filters. An amplifier stage is configured to provide the amplified PWM signals. The die includes two pads configured to be coupled to an external inductor, and a second set of pads configured to provide regulated voltages. An electronic converter circuit is configured to generate the regulated voltages to supply the amplifier stage. The electronic converter circuit includes a control circuit configured to drive electronic switches in response to a second clock signal to regulate the regulated voltages to a respective target value. The die includes a control block to synchronize the switching activity of the electronic switches with the switching activity of the amplifier stage.

An overcurrent detector that includes a sense transistor connected to a sense resistor, a second transistor matched to the sense transistor and connected in parallel to a second resistor, and a voltage comparator coupled to the sense transistor and second resistor. The sense transistor is configured to connect in a same gate and source connection with a driver output transistor. The second transistor and second resistor are configured to receive a current reference and generate a voltage reference. The voltage comparator is configured to compare the voltage reference with a voltage drop across the sense resistor.

A primary circuit outputs, in response to an input signal, a first signal with a first reference potential. A level shift main circuit converts the reference potential of the first signal received from the primary circuit to a second reference potential to output a second signal with the second reference potential. A secondary circuit generates an output signal with the second reference potential using the second signal. At least one rectifying element circuit is provided between the primary circuit and the secondary circuit. At least one of the primary circuit and the secondary circuit includes at least one detection circuit detecting a change in a current flowing through the rectifying element circuit to determine whether a potential corresponding to the second reference potential is lower than or equal to a potential corresponding to the first reference potential.

Embodiments of the present invention provide a switching circuit. The circuit comprises: a charging sub-circuit, which has a first input end and an output end; a switching sub-circuit, which has a first end, a second end, and a control end, wherein the control end of the switching sub-circuit is connected to the output end of the charging sub-circuit; and a function sub-circuit, which is connected to the first end or the second end of the switching sub-circuit, and has a first node, wherein an operating voltage of the first node is higher than an input voltage of an input power supply, the switching sub-circuit comprises one or more NMOS switches, and the first input end of the charging sub-circuit is connected to the first node.