A gate driver communication system includes a cored transformer including a primary coil and a secondary coil configured to receive power signals and uplink data signals from the primary coil; a primary side power signal generator coupled to the primary coil and configured to generate the power signals having a first frequency; a primary side data transmitter coupled to the primary coil and configured to generate the uplink data signals having a second frequency different from the first frequency; and a primary side controller configured to allocate the power signals and the uplink data signals to the primary coil according to a plurality of time slots, wherein the power signals are allocated to first time slots of the plurality of time slots and the uplink data signals are allocated to second times slots of the plurality of time slots.

The upper arm drive circuit for controlling drive of the upper arm switching element of the power conversion device includes: a capacitor disposed between a gate of the upper switching element and the output terminal of the power conversion device; a reverse current prevention circuit that is disposed between a power supply of the power conversion device and the capacitor, and that makes a current flow from a first terminal side of the reverse current prevention circuit connected to the power supply side to a second terminal side of the reverse current prevention circuit connected to the capacitor side and prevents a reverse current from flowing from the second terminal side to the first terminal side; and a switching element for capacitor charging that is turned ON in synchronization with a command signal that turns the upper arm switching element ON.

Aspects of the invention can include a pulse generating means that outputs a set signal and reset signal for driving the high potential side switching element is such that, while either one of the set signal or reset signal is in an on-state as a main pulse signal for putting the high potential side switching element into a conductive state or non-conductive state, the other signal is turned on a certain time after the rise of the main pulse signal, thereby generating a condition in which the set signal and reset signal are both in an on-state.

The present disclosure relates to a power converter configured for limiting switching overvoltage. The power converter comprises a pair of commutation cells. Each commutation cell includes a power electronic switch and a gate driver connected to a gate of the power electronic switch. A reference of the gate driver of a first commutation cell is connected to a ground of the power converter while a reference of the gate driver of a second commutation cell is connected to a collector of the power electronic switch of the first commutation cell. The gate driver of the second commutation cell has no negative voltage power input, either through using a single voltage power supply or by connecting a negative voltage connection of the dual voltage power supply to ground.

A circuit arrangement (1) for operating an electric machine. The circuit arrangement (1) includes at least one high-voltage half-bridge circuit (2), which has a high-side semiconductor switch (3) and a low-side semiconductor switch (4). In each case one gate driver (5, 6) is assigned to the semiconductor switches (3, 4) for actuating said semiconductor switches, and includes a low-voltage controller (7), which actuates the gate drivers (5, 6). A high-voltage controller (11) senses output signals (AS) of the gate drivers (5, 6) and transmits at least the sensed output signals (AS) to the low-voltage controller (7) using a data bus (12).

The present invention relates in a first aspect to a regulated high side gate driver circuit for power transistors. The regulated high side gate driver circuit comprises a gate driver powered by a floating voltage regulator which comprises a linear regulating device.

In accordance with one or more aspects of the disclosed embodiments, a drive circuit having a source of modulation for producing a modulated signal, a level shifter configured to receive the modulated signal and produce a level-shifted driver signal, an inverter circuit configured to receive the level-shifted driver signal and produce a MOSFET control signal, and at least one p-channel metal oxide semiconductor field effect transistor (MOSFET) configured to receive the MOSFET control signal and modulate an application of high current to a load, where the MOSFET control signal is supplied directly to the p-channel MOSFET through the inverter circuit.

A high voltage integrated circuit device suppresses the quantity of holes that are implanted due to a negative voltage surge, thus preventing malfunction and destruction of a high side circuit. A p.sup.−-type aperture portion has a gap portion in an n-type well region that is a voltage resistant region, penetrating the n-type well region to reach a p-type substrate, so as to enclose an n-type well region that is a high potential region.

System and method for controlling one or more switches. The system includes a first converting circuit, a second converting circuit, and a signal processing component. The first converting circuit is configured to convert a first current and generate a first converted voltage signal based on at least information associated with the first current. The second converting circuit is configured to convert a second current and generate a second converted voltage signal based on at least information associated with the second current. The signal processing component is configured to receive the first converted voltage signal and the second converted voltage signal and generate an output signal based on at least information associated with the first converted voltage signal and the second converted voltage signal.

A circuit is disclosed. The circuit includes a current detecting FET, configured to generate a current signal indicative of the value of the current flowing therethrough, an operational transconductance amplifier (OTA) configured to output a current in response to the voltage of the current signal, and a resistor configured to receive the current and to generate a voltage in response to the received current, where the generated voltage is indicative of the value of the current flowing through the current detecting FET. The current detecting FET is configured to become nonconductive in response to the generated voltage indicating that the current flowing through the current detecting FET is greater than a threshold.