A switching circuit comprising a transistor (23) and a drive component both for controlling the transistor and also for limiting the power supply current (Ia) suppled to a load (22), the drive component being arranged both to receive a control voltage (V.sub.H) and also: when the control voltage (VH) is disconnection signal, to generate a drive voltage (V.sub.p) that causes the transistor to occupy a non-conductive state; when the control voltage (VH) is a connection signal and the power supply current (Ia) cannot reach a predefined current threshold, to generate drive voltage (V.sub.p) that causes the transistor to occupy saturated conditions; and when the control voltage (VH) is a connection signal and the power supply current (Ia) can reach a predefined current threshold, to generate a drive voltage (V.sub.p) that causes the transistor to occupy linear conditions, such that the power supply current is regulated so that it does not exceed the predefined current threshold.

A gate driver communication system includes a cored transformer including a primary coil and a secondary coil configured to receive power signals and uplink data signals from the primary coil; a primary side power signal generator coupled to the primary coil and configured to generate the power signals having a first frequency; a primary side data transmitter coupled to the primary coil and configured to generate the uplink data signals having a second frequency different from the first frequency; and a primary side controller configured to allocate the power signals and the uplink data signals to the primary coil according to a plurality of time slots, wherein the power signals are allocated to first time slots of the plurality of time slots and the uplink data signals are allocated to second times slots of the plurality of time slots.

Switch circuitry including an input terminal (1), said input terminal connected to the base of a first transistor (Q1) via a first resistor R3, said first transistor being an NPN Bipolar Gate Transistor (Q1), further comprising a second resistor (R5) connected between the base of said first transistor Q1 and ground, and including an output line or terminal (3) connected to the collector of said first transistor (Q1), and wherein the emitter of said first transistor (Q1) is connected to ground (earth), said circuitry further including a second transistor (Q2), said second transistor being a PNP Bipolar Gate Transistor, wherein the collector of said second transistor (Q2) is connected via a third resistor (R8) to the base of said first transistor (Q1), and the emitter of said second transistor Q2 is connected to said input terminal (1), and wherein the emitter of said second transistor (Q2) is additionally connected to the base of said second transistor Q2 via a fourth resistor R11; and the base of said second transistor (Q2) being additionally connected to the output terminal (3) via a fifth resistor (R10) and a diode (D1).

A power supply circuit includes an inductor, a power transistor configured to control an inductor current flowing through the inductor, and an integrated circuit driving the power transistor. The integrated circuit includes a first terminal that receives a power supply voltage for operating the integrated circuit, generated according to a variation in the inductor current, a second terminal to which a control electrode of the power transistor is coupled, a first drive circuit configured to drive the power transistor via the second terminal during a first time period to turn on the power transistor, and a second drive circuit configured to drive the power transistor via the second terminal during a second time period to turn on the power transistor, the second time period including at least a part of the first time period, driving capability of the second drive circuit being lower than that of the first drive circuit.

Embodiments of this application relate to the field of electricity, and disclose a drive circuit. In some embodiments of this application, the drive circuit includes a low-side driver module and a delay module, the delay module is configured to output a delay signal of preset duration to the low-side driver module in a case that a control module is being reset; and the low-side driver module is configured to: according to on the delay signal of preset duration, maintain a first state within the preset duration, the first state being the same as a second state; where the second state is a working state of the low-side driver module before the control module is reset, and the second state includes being on or off. The embodiments can help avoid safety hazards caused by unexpected disconnection of a drive signal of the control module.

The present disclosure relates to a power converter configured for limiting switching overvoltage. The power converter comprises a pair of commutation cells. Each commutation cell includes a power electronic switch and a gate driver connected to a gate of the power electronic switch. A reference of the gate driver of a first commutation cell is connected to a ground of the power converter while a reference of the gate driver of a second commutation cell is connected to a collector of the power electronic switch of the first commutation cell. The gate driver of the second commutation cell has no negative voltage power input, either through using a single voltage power supply or by connecting a negative voltage connection of the dual voltage power supply to ground.

A circuit arrangement (1) for operating an electric machine. The circuit arrangement (1) includes at least one high-voltage half-bridge circuit (2), which has a high-side semiconductor switch (3) and a low-side semiconductor switch (4). In each case one gate driver (5, 6) is assigned to the semiconductor switches (3, 4) for actuating said semiconductor switches, and includes a low-voltage controller (7), which actuates the gate drivers (5, 6). A high-voltage controller (11) senses output signals (AS) of the gate drivers (5, 6) and transmits at least the sensed output signals (AS) to the low-voltage controller (7) using a data bus (12).

A circuit is disclosed. The circuit includes a current detecting FET, configured to generate a current signal indicative of the value of the current flowing therethrough, an operational transconductance amplifier (OTA) configured to output a current in response to the voltage of the current signal, and a resistor configured to receive the current and to generate a voltage in response to the received current, where the generated voltage is indicative of the value of the current flowing through the current detecting FET. The current detecting FET is configured to become nonconductive in response to the generated voltage indicating that the current flowing through the current detecting FET is greater than a threshold.

In a semiconductor device, a high-side potential determination circuit outputs an event signal when a high-side reference potential detected by a high-side potential detection circuit rises. If at that time an input logic signal for controlling a high side is at a low (L) level, a pulse generation circuit regenerates a reset signal for a high-side drive circuit. When the input logic signal for controlling the high side is at the L level and the event signal is inputted, an overcurrent detection determination circuit makes an overcurrent detection signal from an overcurrent detection circuit invalid. When the event signal is not inputted, the overcurrent detection determination circuit makes the overcurrent detection signal valid.

Disclosed examples include integrated circuits, output driver circuits and protection circuits to protect an output transistor connected between a driver output node and a first intermediate node, including a resistor connected between the output node and a gate terminal of the output transistor, a diode connected between a second intermediate node and the output transistor gate terminal, and a switching device to electrically couple the second intermediate node with a reference node to turn on the output transistor to allow a second transistor to control a voltage of the output node when a control signal is in a first state, and to disconnect the second intermediate node from the reference node to prevent current flow through the resistor to control a gate voltage of the output transistor when the control signal is in a different second state.