An I/O cell comprising a first set of driver stages comprising, each driver stage of the first set comprising a high side switch controllable to couple an I/O node of the I/O cell to a first high voltage supply node and a low side switch controllable to couple the I/O node of the I/O cell to a first low voltage supply node. The I/O cell further comprising a second set of driver stages, each driver stage of the second set comprising a high side switch controllable to couple the I/O node of the I/O cell to a second high voltage supply node and a low side switch controllable to couple the I/O node of the I/O cell to a second low voltage supply node. The switches of the first set of driver stages are controllable independently of the switches of the second set of driver stages.

A drive circuit includes: a control section generating a control signal; a first level shift section raising a level of a signal from the control section; a high side drive section controlling a semiconductor device; and a second level shift section lowering a level of a signal from the high side drive section for input to the control section. The high side drive section has an error detection section maintaining an output of an error detection signal when the semiconductor device is in an error status until a release signal is input, the control section has an error handling section outputting the release signal to the high side drive section via the first level shift section when the error detection signal is input via the second level shift section, and the error detection section stops the output of the error detection signal when the release signal is input.

A switching converter circuit for switching one end of an inductor therein between plural voltages according to a pulse width modulation (PWM) signal to convert an input voltage to an output voltage. The switching converter circuit has a driver circuit including a high side driver, a low side driver, a high side sensor circuit, and a low side sensor circuit. The high side sensor circuit is configured to sense a gate-source voltage of a high side metal oxide semiconductor field effect transistor (MOSFET), to generate a low side enable signal for enabling the low side driver to switch a low side MOSFET according to the PWM signal. The low side sensor circuit is configured to sense a gate-source voltage of a low side MOSFET, to generate a high side enable signal for enabling the high side driver to switch a high side MOSFET according to the PWM signal.

This application discloses a chip and a signal level shifter circuit for use on a mobile terminal such as a charger or an adapter. The chip is co-packaged with a first silicon-based driver die and a second silicon-based driver die that are manufactured by using a BCD technology, and a first gallium nitride die and a second gallium nitride die that are manufactured by using a gallium nitride technology. A first silicon-based circuit is integrated on the first silicon-based driver die, a second silicon-based circuit is integrated on the second silicon-based driver die, and a high-voltage resistant gallium nitride circuit is integrated on the first gallium nitride die. In this way, it can be ensured that a second low-voltage silicon-based driver die manufactured by using a low-voltage BCD technology is not damaged by a high input voltage, thereby reducing costs of the chip.

A voltage source converter has a half bridge (18) with two current valves (19, 20) connected in series and an arrangement configured to carry out voltage measurements for determining a value of the DC voltage between opposite poles (21, 22) of a DC side of the converter. Each current valve comprises a semiconductor device (23, 24) controlled by an associated gate drive member (29, 30), each forming gate drive parts of one gate drive unit (28) in common to both current valves. The gate drive unit (28) comprises an isolated two-way communication link (33) between the gate drive members. The arrangement is included in the gate drive unit and configured to measure the entire DC voltage between said opposite poles (21, 22). A converter control device (31) calculates and sends control signals to the gate drive unit based on the result of the voltage measurement.

A circuit is disclosed. The circuit includes a current detecting FET, configured to generate a current signal indicative of the value of the current flowing therethrough, an operational transconductance amplifier (OTA) configured to output a current in response to the voltage of the current signal, and a resistor configured to receive the current and to generate a voltage in response to the received current, where the generated voltage is indicative of the value of the current flowing through the current detecting FET. The current detecting FET is configured to become nonconductive in response to the generated voltage indicating that the current flowing through the current detecting FET is greater than a threshold.

Provided is a current control device capable of continuing feedback control for a solenoid in normal feedback control while preventing occurrence of an unintended valve operation due to flow of a reverse current.

An active gate driver suitable for activating an electronic switch of an electric motor. The active gate driver comprises a pull up branch, a pull down branch and a current and voltage feedback from an output of the active gate driver to at least one input of the active gate driver, wherein the current and voltage feedback is common to both the pull up branch and the pull down branch.

An electronic module for a half-bridge circuit includes a base substrate with an insulating layer between a first metal layer and a second metal layer. A trench formed through the first metal layer electrically isolates first, second, and third portions of the first metal layer from one another. A high-side switch includes an enhancement-mode transistor and a depletion-mode transistor. The depletion-mode transistor includes a III-N material structure on an electrically conductive substrate. A drain electrode of the depletion-mode transistor is connected to the first portion, a source electrode of the enhancement-mode transistor is connected to the second portion, a drain electrode of the enhancement-mode transistor is connected to a source electrode of the depletion-mode transistor, a gate electrode of the depletion-mode transistor is connected to the electrically conductive substrate, and the electrically conductive substrate is connected to the second portion.

A power electronics device has a first power semiconductor switch and a driver circuit and enables a supply of electrical voltage to a driver circuit. An auxiliary circuit arrangement has a supply capacitor, an auxiliary capacitor, a normally off auxiliary semiconductor switch, a diode and a bootstrap diode. The auxiliary semiconductor switch is connected to a reference potential connection of the first power semiconductor switch via a connection point, starting from the connection point, a series connection of the diode, a second connection point and the auxiliary capacitor is arranged in parallel with the auxiliary semiconductor switch. When the auxiliary semiconductor switch is in the off state, the auxiliary capacitor is charged by the flow of current through the first power semiconductor switch.