Provided is a phase-locked loop circuit, a method for configuring the same, and a communication device. The phase-locked loop circuit includes a phase-locked loop main circuit and a phase temperature compensation circuit. The phase temperature compensation circuit includes at least one phase delay unit connected to the phase-locked loop main circuit and configured to generate a phase shift as a result of a temperature change for cancelling out a phase shift generated by the phase-locked loop main circuit as a result of a temperature change.

A vibrator device includes a vibration element including a vibration portion and a fixed portion, a supporting member to which the fixed portion is attached to support the vibration element, and a first substrate to which the supporting member is attached, the supporting member includes a attaching portion attached to the first substrate, and A1≥A2 is satisfied in a case where an area of a rectangular region including the fixed portion is A1 and an area of a rectangular region including the attaching portion is A2 in a plan view seen from a thickness direction of the vibration element.

The present disclosure relates to a method for controlling a device comprising an oscillation circuit, configured to provide a clock signal to a radio frequency circuit, and an antenna, in which the enabling of the passage of the signal from the circuit to the antenna is delayed with respect to an instant from which a power amplifier of the circuit is enabled.

In an example, a system includes a BAW resonator. The system also includes a first heater configured to heat the BAW resonator, where the first heater is controlled by a first control loop. The system includes a circuit coupled to the BAW resonator. The system also includes a second heater configured to heat the circuit, where the second heater is controlled by a second control loop.

A circuit device includes an oscillation circuit configured to generate an oscillation signal using a resonator, a temperature sensor circuit configured to output temperature detection data, a temperature compensation circuit configured to perform, based on the temperature detection data, temperature compensation on an oscillation frequency of the oscillation signal, a memory configured to store correction data for correcting the temperature detection data to obtain a temperature, and an interface circuit configured to output the temperature detection data and the correction data.

The present disclosure relates to an electronic device comprising a first capacitor and a quartz crystal coupled in series between a first node and a second node; an inverter coupled between the first and second nodes; a first variable capacitor coupled between the first node and a third node; and a second variable capacitor coupled between the second node and the third node.

A system of free running oscillators synchronized to the lowest frequency running one and following PVT variation generates a system clock. A method is particularly applicable to clock relatively small clock domains within a multi-core chip containing thousands of cores, and where the clock domain encompasses one or more cores and additional logic blocks. The resulting system clock is divided by 2.sup.k using latches or flip-flops to achieve a symmetric 50-50 duty cycle of the system clock. Further, such PVT insensitive system clock can be used as a reference for a PLL or DLL generated clock for the domain.

A system of free running oscillators synchronized to the lowest frequency running one and following PVT variation generates a system clock. A method is particularly applicable to clock relatively small clock domains within a multi-core chip containing thousands of cores, and where the clock domain encompasses one or more cores and additional logic blocks. The resulting system clock is divided by 2.sup.k using latches or flip-flops to achieve a symmetric 50-50 duty cycle of the system clock. Further, such PVT insensitive system clock can be used as a reference for a PLL or DLL generated clock for the domain.

Embodiments of the present application provide an oscillator and a clock generation circuit. The oscillator includes: a first ring topology, including a plurality of first inverters connected end to end, and configured to transmit an oscillation signal at a first transmission speed; and a second ring topology, including a plurality of second inverters connected end to end, and configured to transmit the oscillation signal at a second transmission speed, wherein the present application, the first ring topology is electrically connected to the second ring topology, and the second transmission speed is less than the first transmission speed.

There is provided a semiconductor device comprising: a first inverter circuit (11) connected in parallel to a crystal vibrating element (X1); a second inverter circuit (12) connected to the first inverter circuit (11) so as to share an input therewith, and outputting an oscillation signal; and a wave filter (14) connected to the second inverter circuit (12) and having a passband that is determined in advance and includes an oscillation frequency of the oscillation signal.