H03L7/02

SYSTEMS AND METHODS FOR STORING FREQUENCY INFORMATION FOR SYSTEM CALIBRATION/TRIMMING
20180059171 · 2018-03-01 · ·

Embodiments of the present disclosure include a microcontroller with a frequency test circuit, a device-under-test (DUT) input, and a calculation engine circuit. The calculation engine circuit is configured to compare a measured frequency from the frequency test circuit measured from the DUT input to a reference frequency stored in memory, and, based on the comparison, adjust frequency of the DUT generating the DUT input.

Digitally Reconfigurable Ultra-High Precision Internal Oscillator
20180054204 · 2018-02-22 ·

A system, method and apparatus for tuning an internal oscillator to a desired frequency F1 is shown and uses an RC delay element that comprises a resistor, a capacitor and a comparator. The method includes receiving a clock signal from an oscillator to be tuned, triggering charging of the RC delay element, and N clock cycles after triggering the charging, the method determines whether the charge on the precision RC delay element is higher than or lower than a reference voltage. Correction to the clock frequency is based on the results.

Digitally Reconfigurable Ultra-High Precision Internal Oscillator
20180054204 · 2018-02-22 ·

A system, method and apparatus for tuning an internal oscillator to a desired frequency F1 is shown and uses an RC delay element that comprises a resistor, a capacitor and a comparator. The method includes receiving a clock signal from an oscillator to be tuned, triggering charging of the RC delay element, and N clock cycles after triggering the charging, the method determines whether the charge on the precision RC delay element is higher than or lower than a reference voltage. Correction to the clock frequency is based on the results.

Digitally reconfigurable ultra-high precision internal oscillator
09825637 · 2017-11-21 · ·

A system, method and apparatus for tuning an internal oscillator to a desired frequency F1 is shown and uses an RC delay element that comprises a resistor, a capacitor and a comparator. The method includes receiving a clock signal from an oscillator to be tuned, triggering charging of the RC delay element, and N clock cycles after triggering the charging, the method determines whether the charge on the precision RC delay element is higher than or lower than a reference voltage. Correction to the clock frequency is based on the results.

Digitally reconfigurable ultra-high precision internal oscillator
09825637 · 2017-11-21 · ·

A system, method and apparatus for tuning an internal oscillator to a desired frequency F1 is shown and uses an RC delay element that comprises a resistor, a capacitor and a comparator. The method includes receiving a clock signal from an oscillator to be tuned, triggering charging of the RC delay element, and N clock cycles after triggering the charging, the method determines whether the charge on the precision RC delay element is higher than or lower than a reference voltage. Correction to the clock frequency is based on the results.

CR oscillation circuit
09716501 · 2017-07-25 · ·

A CR oscillation circuit includes inverters forming a loop for circulation of a signal, CR time constant circuits inserted into the loop for delaying the signal, each circuit having a capacitor, a plurality of resistance elements, and a transmission gate that selects an arbitrary resistance element of the plurality of resistance elements as a charge and discharge path of the capacitor, and a gate voltage generation circuit as means for outputting a gate voltage for controlling ON/OFF of each transmission gate that outputs a constant voltage in conjunction of a threshold voltage of a field-effect transistor as a gate voltage for turning ON the transmission gate.

CR oscillation circuit
09716501 · 2017-07-25 · ·

A CR oscillation circuit includes inverters forming a loop for circulation of a signal, CR time constant circuits inserted into the loop for delaying the signal, each circuit having a capacitor, a plurality of resistance elements, and a transmission gate that selects an arbitrary resistance element of the plurality of resistance elements as a charge and discharge path of the capacitor, and a gate voltage generation circuit as means for outputting a gate voltage for controlling ON/OFF of each transmission gate that outputs a constant voltage in conjunction of a threshold voltage of a field-effect transistor as a gate voltage for turning ON the transmission gate.

Circuit system adaptively adjusting supply voltage according to temperature and operating method thereof
09705508 · 2017-07-11 · ·

A circuit system includes a current supply module, a voltage supply module and a voltage-controlled oscillator (VCO). The current supply module provides a current adapted to an ambient temperature. The voltage supply module receives the current and generates an adapted voltage according to the current. The VCO receives the adapted voltage and generates an oscillation signal according to the adapted voltage.

Circuit system adaptively adjusting supply voltage according to temperature and operating method thereof
09705508 · 2017-07-11 · ·

A circuit system includes a current supply module, a voltage supply module and a voltage-controlled oscillator (VCO). The current supply module provides a current adapted to an ambient temperature. The voltage supply module receives the current and generates an adapted voltage according to the current. The VCO receives the adapted voltage and generates an oscillation signal according to the adapted voltage.

Tracking of signals with at least one subcarrier

A system for tracking a received signal with a subcarrier, the received signal representing a carrier signal modulated with a code signal and with a subcarrier signal. The system comprises independent and cooperatively operating loops: a phase lock loop tracking the carrier signal, a subcarrier lock loop tracking the subcarrier signal, and a delay lock loop tracking the code signal. The subcarrier lock loop comprises a first controllable oscillator and a first early-minus-late discriminator generating a control signal for the first controllable oscillator. The delay lock loop comprising a second controllable oscillator and a second arctan discriminator generating a control signal for the second controllable oscillator.