A semiconductor apparatus includes a memory controller and data storage configured to input and output data in synchronization with a clock signal provided from the memory controller. The data storage includes a memory cell array and a data output apparatus configure to output read data from the memory cell array by sensing a logic level of the read data during a low-level period of a first clock, which is an inverted signal of a divided clock of the clock signal, and a low-level period of a second clock, the second clock having a set to phase delay amount from the divided clock.

Systems and methods are described for transmitting and receiving wireless power. In some embodiments, a wireless power transmission system comprises an antenna array comprising a plurality of antennas and a transceiver module configured to receive a plurality of beaconing signals via the antenna array from a wireless client during a beacon cycle. The system also comprises a controller configured to measure a phase of each of the plurality of beaconing signals and determine a transmit phase configuration for each of the antennas, and a transceiver module configured to send signals to the antenna array based on the transmit phase configuration for delivery of wireless power to the wireless client.

Systems and methods are described for transmitting and receiving wireless power. In some embodiments, a wireless power transmission system comprises an antenna array comprising a plurality of antennas and a transceiver module configured to receive a plurality of beaconing signals via the antenna array from a wireless client during a beacon cycle. The system also comprises a controller configured to measure a phase of each of the plurality of beaconing signals and determine a transmit phase configuration for each of the antennas, and a transceiver module configured to send signals to the antenna array based on the transmit phase configuration for delivery of wireless power to the wireless client.

A clock correction circuit in which a correction accuracy of a duty cycle is increased is provided. The clock correction circuit comprises a delay-locked loop circuit configured to receive a first clock signal and generate a second clock signal obtained by delaying the first clock signal; a first duty cycle correction circuit configured to receive the second clock signal and generate a first correction clock signal obtained by correcting a duty cycle of the second clock signal; and a duty cycle detection circuit which includes a second duty cycle correction circuit and an error code generation circuit, wherein the error code generation circuit receives the first correction clock signal, and generates a first error code as to whether to correct the duty cycle of the second clock signal on the basis of the first correction clock signal, the second duty cycle correction circuit generates a second correction clock signal obtained by correcting the duty cycle of the first correction clock signal in response to the first error code, the error code generation circuit generates a second error code as to whether to correct the duty cycle of the second clock signal on the basis of the second correction clock signal, and the first duty cycle correction circuit receives the second error code, and generates a third correction clock signal obtained by correcting the duty cycle of the second clock signal in response to the second error code.

A re-timer device includes transceiver circuitry. The transceiver circuitry includes clock generation circuitry and first receiver circuitry. The clock generation circuitry generates a first clock signal. The first receiver circuitry receives the first clock signal and a first input signal. The first receiver circuitry generates a first frequency offset value based on the first input signal and the first clock signal. The first input signal has a first frequency and the first clock signal has a second frequency different than the first frequency. The first receiver circuitry outputs the first frequency offset value.

A re-timer device includes transceiver circuitry. The transceiver circuitry includes clock generation circuitry and first receiver circuitry. The clock generation circuitry generates a first clock signal. The first receiver circuitry receives the first clock signal and a first input signal. The first receiver circuitry generates a first frequency offset value based on the first input signal and the first clock signal. The first input signal has a first frequency and the first clock signal has a second frequency different than the first frequency. The first receiver circuitry outputs the first frequency offset value.

There is provided with an information processing apparatus. A plurality of functional blocks are in synchronization relationship. Each of a plurality of generation units comprises a counter and a frequency division circuit. The frequency division circuit frequency-divides a reference clock based on a value of the counter. Each of the plurality of generation units supplies a clock generated using the reference clock to a corresponding functional block among the plurality of functional blocks.

There is provided with an information processing apparatus. A plurality of functional blocks are in synchronization relationship. Each of a plurality of generation units comprises a counter and a frequency division circuit. The frequency division circuit frequency-divides a reference clock based on a value of the counter. Each of the plurality of generation units supplies a clock generated using the reference clock to a corresponding functional block among the plurality of functional blocks.

A current stimulator includes a first current generation circuit configured to generate a first current, injectable into a cranial nerve cell, through a current mirroring based on a plurality of transistor pairs; and a second current generation circuit, driven by a clock, configured to generate a second current smaller than the first current by controlling a charge rate based on a voltage difference between terminals of a capacitor. A first output impedance of the first current generation circuit and a second output impedance of the second current generation circuit have a magnitude greater than or equal to a predetermined ratio to a load impedance corresponding to the cranial nerve cell.

A current stimulator includes a first current generation circuit configured to generate a first current, injectable into a cranial nerve cell, through a current mirroring based on a plurality of transistor pairs; and a second current generation circuit, driven by a clock, configured to generate a second current smaller than the first current by controlling a charge rate based on a voltage difference between terminals of a capacitor. A first output impedance of the first current generation circuit and a second output impedance of the second current generation circuit have a magnitude greater than or equal to a predetermined ratio to a load impedance corresponding to the cranial nerve cell.