Systems and methods associated with reducing clock skew are disclosed. In some exemplary embodiments, there is provided circuitry associated with lock loop circuits such as a phase lock loop (PLL). Such circuitry may comprise output clock tree circuitry and phase averaging circuitry. In other exemplary embodiments, there is provided circuitry associated with delay lock loop (DLL) circuits. Such circuitry may comprise output clock tree circuitry and/or phase averaging circuitry.

A semiconductor device may include a division control circuit and a latch circuit. The division control circuit may be configured to divide an external clock to generate a first preliminary divided clock and a second preliminary divided clock. The division control circuit may be configured to output the first and second preliminary divided clocks or any one of the first and second preliminary divided clocks as first and second divided clocks. The latch circuit may be configured to latch an external control signal in response to the first and second divided clocks and configured to output latched signals as first and second latch control signals.

A semiconductor device may include a division control circuit and a latch circuit. The division control circuit may be configured to divide an external clock to generate a first preliminary divided clock and a second preliminary divided clock. The division control circuit may be configured to output the first and second preliminary divided clocks or any one of the first and second preliminary divided clocks as first and second divided clocks. The latch circuit may be configured to latch an external control signal in response to the first and second divided clocks and configured to output latched signals as first and second latch control signals.

A subsampling motion detector configured to detect motion information of an object under measurement receives a first wireless radio frequency (RF) signal and transmits a second wireless RF signal, the first wireless RF signal being generated by reflecting the second wireless RF signal from the object. The subsampling motion detector includes a controllable oscillator outputting an oscillation signal, wherein the first wireless RF signal is injected to the controllable oscillator for controlling the controllable oscillator through injecting locking. The subsampling motion detector further including a subsampling phase detector (SSPD) generating a control signal according to the oscillation signal generated by the controllable oscillator and a reference frequency, the SSPD outputting the control signal to the controllable oscillator for controlling the controllable oscillator, the oscillation signal of the controllable oscillator being locked to a multiple of the reference frequency and the control signal representing the motion information of the object.

A subsampling motion detector configured to detect motion information of an object under measurement receives a first wireless radio frequency (RF) signal and transmits a second wireless RF signal, the first wireless RF signal being generated by reflecting the second wireless RF signal from the object. The subsampling motion detector includes a controllable oscillator outputting an oscillation signal, wherein the first wireless RF signal is injected to the controllable oscillator for controlling the controllable oscillator through injecting locking. The subsampling motion detector further including a subsampling phase detector (SSPD) generating a control signal according to the oscillation signal generated by the controllable oscillator and a reference frequency, the SSPD outputting the control signal to the controllable oscillator for controlling the controllable oscillator, the oscillation signal of the controllable oscillator being locked to a multiple of the reference frequency and the control signal representing the motion information of the object.

In some embodiments, a tight loop mode is provided in which most, if not all of, the clock distribution circuitry may be bypassed during an initial frequency lock stage.

In some embodiments, a tight loop mode is provided in which most, if not all of, the clock distribution circuitry may be bypassed during an initial frequency lock stage.

A biased impedance circuit, an impedance adjustment circuit, and an associated signal generator are provided. The biased impedance circuit is coupled to a summation node and applies a biased impedance to the summation node. A periodic input signal is received at the summation node. The biased impedance circuit includes a switching circuit for receiving an output window signal, wherein a period of the output window signal is shorter than a period of the periodic input signal. The switching circuit includes a low impedance path and a high impedance path. The low impedance sets the biased impedance to a first impedance when the output window signal is at a first voltage level. The high impedance path sets the biased impedance to a second impedance when the output window signal is at a second voltage level. The first impedance is less than the second impedance.

The present disclosure provides an adaptive adjustment circuit in a computer chip having a voltage-controlled oscillator (VCO) and a processor. The adaptive adjustment circuit comprises a frequency difference acquisition module to generate a frequency difference signal based on a first difference between an oscillation frequency of the VCO and a target frequency. The adaptive adjustment circuit also includes a power module to supply a working voltage to the VCO and the processor, adjust the working voltage based on the frequency difference signal, and supply the adjusted working voltage to the VCO and the processor.

The present disclosure provides an adaptive adjustment circuit in a computer chip having a voltage-controlled oscillator (VCO) and a processor. The adaptive adjustment circuit comprises a frequency difference acquisition module to generate a frequency difference signal based on a first difference between an oscillation frequency of the VCO and a target frequency. The adaptive adjustment circuit also includes a power module to supply a working voltage to the VCO and the processor, adjust the working voltage based on the frequency difference signal, and supply the adjusted working voltage to the VCO and the processor.