The present disclosure provides a circuit and method for expanding the lock range of injection-locked oscillators. The circuit includes N injection-locked oscillators and a lock detector, where the lock detector includes an alignment monitor, a clock selector, and N self-samplers. A pulse reference signal is inputted into the N injection-locked oscillators, and the output of each injection-locked oscillator is connected to the clock selector and the corresponding self-sampler. The self-samplers sample the outputs of the N injection-locked oscillators and output the sampling results to the alignment monitor. The alignment monitor monitors the sampling results, determines the locking conditions of the injection-locked oscillators, and turns off the unlocked oscillators. The clock selector selects a locked oscillator and transmits the output of the locked oscillator as a system lock.

A low-power clock generation circuit has a phase generator that receives an input clock signal and uses the input clock signal to generate multiple intermediate clock signals with different phase shifts, a phase rotator circuit that outputs phase-adjusted clock signals, a frequency doubler circuit that receives a plurality of the phase-adjusted clock signals and outputs two frequency-doubled clock signals having a 180° phase difference, and a quadrature clock generation circuit that receives the two frequency-doubled clock signals and provides four output signals that include in-phase and quadrature versions of the two frequency-doubled clock signals.

A system and corresponding method that achieves coherency and deterministic latency (CDL) autonomously upon power on is disclosed. The system, for example, a multi-channel RF system, may require CDL with respect to the digital-to-analog converters (DACs) and analog-to-digital converters (ADCs) assigned to the channels in the system. CDL is achieved through a timed combination of external reference and synchronization signals, resetting and disabling of various clock dividers, and enabling clock generation. In addition to synchronizing all of the clocks, the data acquisition sequence must be synchronized across all of the channels, whether they are on chips, cards, or chassis. Data acquisition synchronization may be implemented using an initiator/target or a wired OR mode configuration.

A system and corresponding method that achieves coherency and deterministic latency (CDL) autonomously upon power on is disclosed. The system, for example, a multi-channel RF system, may require CDL with respect to the digital-to-analog converters (DACs) and analog-to-digital converters (ADCs) assigned to the channels in the system. CDL is achieved through a timed combination of external reference and synchronization signals, resetting and disabling of various clock dividers, and enabling clock generation. In addition to synchronizing all of the clocks, the data acquisition sequence must be synchronized across all of the channels, whether they are on chips, cards, or chassis. Data acquisition synchronization may be implemented using an initiator/target or a wired OR mode configuration.

Systems and methods for integrating injection-locked oscillators into transceiver arrays are disclosed. In one aspect, there is provided an injection-locked oscillator (ILO) distribution system including a master clock generator configured to generate a master clock signal. The ILO distribution system also includes an ILO distribution circuit including an ILO and configured to receive the master clock signal. The ILO is configured to generate a reference clock signal based on the master clock signal. The ILO distribution circuit is further configured to generate an output signal indicative of an operating frequency of the ILO. The ILO distribution system further includes an injection-locked detector (ILD) configured to receive the master clock signal and the output signal. The ILD is further configured to determine whether the ILO is in a locked state or in an unlocked state based on the master clock signal and the output signal.

A novel phase locked loop design utilizing novel phase-frequency detector, charge pump, loop filter and voltage controlled oscillator is disclosed. The phase-frequency detector includes a dual reset D-flip flop for use in multi-GHz phase locked loops. Traditional dead zone issues associated with phase frequency detector are improved/addressed by use with a charge transfer-based PLL charge pump.

A novel phase locked loop design utilizing novel phase-frequency detector, charge pump, loop filter and voltage controlled oscillator is disclosed. The phase-frequency detector includes a dual reset D-flip flop for use in multi-GHz phase locked loops. Traditional dead zone issues associated with phase frequency detector are improved/addressed by use with a charge transfer-based PLL charge pump.

An injection-locked oscillator includes an oscillator and an injection circuit. The oscillator includes a first oscillation node through which a first oscillation signal is output and a second oscillation node through which a second oscillation signal is output, the second oscillation signal having a phase opposite to that of the first oscillation signal. The injection circuit provides an injection current between the first oscillation node and the second oscillation node according to a reference signal. The injection circuit includes a charging element configured to be charged or discharged in response to a reference signal and to provide the injection current between the first oscillation node and the second oscillation node.

An injection-locked oscillator includes an oscillator and an injection circuit. The oscillator includes a first oscillation node through which a first oscillation signal is output and a second oscillation node through which a second oscillation signal is output, the second oscillation signal having a phase opposite to that of the first oscillation signal. The injection circuit provides an injection current between the first oscillation node and the second oscillation node according to a reference signal. The injection circuit includes a charging element configured to be charged or discharged in response to a reference signal and to provide the injection current between the first oscillation node and the second oscillation node.

A multiplication injection locked oscillator (MIILO) circuitry includes a ring injection locked oscillator (ILO) circuitry that outputs clock signals, a first switching circuitry and a second switching circuitry. The ring ILO circuitry includes a first path having first delay stages, and a second path having a second delay stages. The first switching circuitry is connected to the first path and a voltage supply node. The first switching circuitry receives a first control signal and a second control signal and selectively connects the voltage supply node to the first path. The second switching circuitry is connected to the second path and a reference voltage node. The second switching circuitry receives the first control signal and the second control signal and selectively connects the reference voltage node to the second path.